參數(shù)資料
型號: W234
英文描述: Clocks and Buffers
中文描述: 時鐘和緩沖器
文件頁數(shù): 7/14頁
文件大?。?/td> 160K
代理商: W234
W234
Document #: 38-07232 Rev. *B
Page 7 of 14
Timing Diagrams
t
POWERUP
t
POWERDN
t
STOP
t
ON
t
CLKON
t
CLKOFF
t
CLKSETL
PWR_DWN#
CLK0/CLK0#
CLK1/CLK1#
Power-Down Exit and Entry
Output Enable Control
STOP#
output clock
not specified
glitches may
clock enabled
and glitch free
clock output settled within
50 ps of the phase before
disabled
CLK0/CLK0#
CLK1/CLK1#
Figure 5. State Transition Timing Diagrams.
t
MULT
MULT0 and/or MULT1 and/or MULT2
CLK0/CLK0#
CLK1/CLK1#
Figure 6. Multiply Transition Timing.
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