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參數(shù)資料
| 型號： | W234 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 160K |
| 代理商： | W234 |
W234
Document #: 38-07232 Rev. *B
Page 2 of 14
Pin Definitions
Pin Name
REFCLK
Pin
No.
2
Pin
Type
I
Pin Description
Reference Clock Input:
Reference clock input, normally supplied by a system
frequency synthesizer (Cypress W133).
Phase Detector Input 0:1:
The phase difference between this signal and SYN-
CLKN is used to synchronize the Rambus Channel Clock with the system clock.
Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory
controller. If the Gear Ratio Logic is not used, this pin would be connected to
ground.
Phase Detector Input 0:1:
The phase difference between this signal and PCLKM
is used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If the Gear Ratio Logic is not used, this pin would be connected to ground.
Clock Output Enable:
When this input is driven to active LOW, it disables the
differential Rambus Channel clocks.
Active LOW Power-Down:
When this input is driven to active LOW, it disables
the differential Rambus Channel clocks and places the W234 in Power-Down
mode.
PLL Multiplier Select:
These inputs select the PLL prescaler and feedback divid-
ers to determine the multiply ratio for the PLL for the input REFCLK.
PCLKM0:1
5, 10
I
SYNCLKN0:1
4, 9
I
STOP#
13
I
PWR_DWN#
14
I
MULT 0:2
17, 16, 15
I
CLK0, CLK0#,
CLK1, CLK1#
S0, S1, S2
23, 24, 20,
19
28, 27, 26
O
Complementary Output Clock:
Differential Rambus Channel clock outputs.
I
Mode Control Input:
These inputs control the operating mode of the W234.
VDDIR
VDDIPD
1
RefV
RefV
Reference for Refclk:
Voltage reference for input reference clock.
Reference for Phase Detector:
Voltage reference for phase detector inputs and
STOP#.
Power Connection:
Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection:
Connect all ground pins to the common system ground
plane.
12
VDD
3, 7, 11, 21,
22
6, 8, 18, 25
P
GND
G
MULT1
0
0
1
1
0
0
1
1
MULT0
0
0
0
0
1
1
1
1
A
4
9
6
TBD
8
16
8
TBD
MULT2
0
1
0
1
0
1
0
1
B
1
2
1
TBD
3
3
1
TBD
S1
0
0
1
0
0
1
1
S0
0
1
1
0
1
1
0
MODE
Normal
Bypass
Test
Vendor Test A
Vendor Test B
Reserved
Output Test (OE)
S2
0
0
0
1
1
1
X
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