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參數(shù)資料
| 型號： | W234 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 160K |
| 代理商： | W234 |
W234
Document #: 38-07232 Rev. *B
Page 4 of 14
Phase Detector Signals
The DRCG Phase Detector (
φ
D
) receives two inputs from the
core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M
and N dividers in the core logic are chosen so that the frequen-
cies of PCLKM and SYNCLKN are identical. The Phase De-
tector (
φ
D
) detects the phase difference between the two input
clocks, and drives the DRCG Phase Aligner to null the input
phase error through the distributed loop. When the loop is
locked, the input phase error between PCLKM and SYNCLKN
is within the specification t
ERR,PD
given in
Table 13
after the
lock time given in the State Transition Section.
The Phase Detector (
φ
D
) aligns the rising edge of PCLKM to
the rising edge of SYNCLKN. The duty cycle of the phase de-
tector input clocks will be within the specification DC
IN,PD
giv-
en in
Table 12
. Because the duty cycles of the two phase de-
tector input clocks will not necessarily be identical, the falling
edges of PCLKM and SYNCLKN may not be aligned when the
rising edges are aligned.
The voltage levels of the PCLKM and SYNCLKN signals are
determined by the controller. The pin VDDIPD is used as the
voltage reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PCLKM and SYN-
CLKN are not used, those inputs must be grounded.
Selection Logic
Table 1
shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLClk=Refclk*A/B.
Table 2
shows the logic for enabling the clock outputs, using
the STOP# input signal. When STOP# is HIGH, the DRCG is
in its normal mode, and CLK and CLK# are complementary
outputs following the Phase Aligner output (PAclk). When
STOP# is LOW, the DRCG is in the Clk Stop mode, the output
clock drivers are disabled (set to Hi-Z), and the CLK and CLK#
settle to the DC voltage V
X,STOP
as given in
Table 13
. The level
of V
X,STOP
is set by an external resistor network.
Table 3
shows the logic for selecting the Bypass and Test
modes. The select bits, S0, S1, and S2 control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the REFCLK input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the CLK and CLK# outputs are put into a high-
impedance state (Hi-Z). This can be used for component test-
ing and for board-level testing.
Figure 3. DDLL Including Details of DRCG.
W234
Refclk
W158
W159
W161
W167B
PLL
Phase
Align
D
4
DLL
RAC
RMC
M N
Gear
Ratio
Logic
Pclk
Busclk
Synclk
P
S
S0/S1/S2 STOP#
CY2210-2
CY2210-3
W133
Table 1. PLL Divider Selection
MULT0
MULT1
0
0
0
0
1
1
1
1
MULT2
0
1
0
1
0
1
0
1
A
4
9
6
B
1
2
1
0
0
1
1
0
0
1
1
TBD
8
3
3
1
16
8
TBD
Table 2. Clk Stop Mode Selection
Mode
Normal
Clk Stop
STOP#
1
0
CLK
PACLK
V
X,STOP
CLK#
PACLK#
V
X,STOP
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