參數(shù)資料
型號(hào)： W234
英文描述： Clocks and Buffers
中文描述： 時(shí)鐘和緩沖器
文件頁數(shù)： 6/14頁
文件大小： 160K
代理商： W234
W234
Document #: 38-07232 Rev. *B
Page 6 of 14
In Clk Stop mode, the clock source is on, but the output is
disabled (STOP# asserted). The VDDIPD reference input may
remain on or may be grounded during the Clk Stop mode. The
VDDIR reference input must remain on during the Clk Stop
mode.
In Normal mode, the clock source is on, and the output is en-
abled.
Table 6
lists the control signals for each state.
Figure 5
shows the timing diagrams for the various transitions
between states, and
Table 7
specifies the latencies of each
state transition. Note that these transition latencies assume
the following:
REFCLK input has settled and meets specification shown
in
Table 12
.
MULT0, MULT1, MULT2, S0, S1, and S2 control signals
are stable.
Test
M
N
L
K
Normal
Power-Down
Clk Stop
D
C
G
A
E
F
H
V
DD
Turn-On
V
DD
Turn-On
V
DD
Turn-On
V
DD
Turn-On
B
J
Figure 4. Clock Source State Diagram.
Table 6. Control Signals for Clock Source States
State
PWR_DWN#
0
1
1
STOP#
X
0
1
Clock
Source
OFF
ON
ON
Output
Buffer
Ground
Disabled
Enabled
Power-Down
Clk Stop
Normal
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