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參數(shù)資料
| 型號： | W6692ACD |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 10/101頁 |
| 文件大小： | 851K |
| 代理商： | W6692ACD |
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W6692A
- 10 -
4. PIN DESCRIPTION
TABLE 4.1 PIN DESCRIPTIONS
Notation
: The suffix
"
#
"
indicates an active LOW signal. In Intel or Motorola bus mode, all
unspecified pins must be left unconnected.
PIN
NAME
PIN
NUMBER
TYP.
FUNCTIONS
PCI Mode (Enabled when CLK toggles)
84
I
PCI Mode
: PCI Clock. All other PCI signals, except
RST#, INTA# are sampled on the rising edge of CLK.
According to PCI 2.1/2.2 specification, CLK is stable at
least 100
μ
S (Trst-clk) before deassertion of RST#.
Intel Bus Mode
: Must be pulled to HIGH.
Motorola Bus Mode
: Must be pulled to LOW.
CLK
AD31-AD0
85, 86, 87, 90,
91, 92, 93, 94,
97, 98, 99, 100,
7, 8, 9, 10, 23,
24, 25, 30, 33,
34, 35, 36, 38,
39, 40, 41, 44,
45, 46, 47
I/O
pins. During the address phase, AD31-0 contains a 32-
bit physical address. During the data phase, AD7-AD0
contains the least significant byte and AD31-AD24
contain the most significant byte.
C/BE3#-
C/BE0#
95, 11, 22, 37
I
Bus command and Byte Enables.
During the address phase of a transaction, they define
the bus command.
During data phase, they are used as Byte Enables.
PAR
21
I/O
Parity is even parity across AD31-AD0 and C/BE3#-
C/BE0#.
FRAME#
12
I
FRAME# is asserted to indicate a bus transaction is
beginning.
TRDY#
14
O
Target Ready indicates W6692A is able to complete
the current data phase of the transaction.
IRDY#
13
I
′
s ability to
complete the current data phase of the transaction.
STOP#
18
O
Stop indicates W6692A is requesting the master to
stop the current transaction.
DEVSEL#
15
O
Device Select indicates W6692A has decoded itself as
the target of the current access.
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