參數(shù)資料
型號(hào)： W6692ACD
英文描述： ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料
文件頁(yè)數(shù)： 41/101頁(yè)
文件大小： 851K
代理商： W6692ACD
W6692A
Publication Release Date: July 2000
- 41 -
Revision A1
GCI slave mode
: connects to U transceiver such as PEB 2091, CH0 used only.
GCI master mode
: connects to PSB 2165 ARCOFI, uses B1, B2, IC1 and IC2 for voice
communication, uses MON1 for programming, uses C/I1 for pins SA-SD access.
7.8.1 GCI Mode C/I0 Channel Handling
The Command/Indication channel 0 carries real-time status information between the W6692A and
another device connected to the GCI bus interface.
One C/I0 channel conveys the commands and indications between a layer 1 device and layer 2
device. This C/I0 channel is accessed via register CIR (in receive direction, layer 1 to layer 2) and
register CIX (in transmit direction, layer 2 to layer 1). The C/I code is 4-bit long.
In the receive direction, the code from layer 1 is continuously monitored, with an interrupt being
generated anytime a change occurs. A new code must be found in two consecutive GCI frames
to be consided valid and to trigger a C/I code change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX is continuously transmitted in the channel.
7.8.2 GCI Mode Monitor Channel Handling
The Monitor channel protocol is a handshake protocol used for high speed information exchange
between the W6692A and other devices. The Monitor channel is necessary for:
Programming and controlling devices attached to the GCI interface.
Data exchange between two microprocessor systems attached to two different devices on one
GCI backplane. Use of the Monitor channel avoids the necessity of a dedicated serial
communication path between two systems.
The Monitor channel operates on an asynchronous basis. While data transfers on the bus take place
synchronized to frame sync, the flow of data is controlled by a handshake procedure using the
Monitor Channel Receiver (MOR) and Monitor Channel Transmit (MOX) bits. When data is placed
into the Monitor channel and the MX bit is activated. This data will be transmitted repeatedly once per
8 KHz frame until the transfer is acknowledged via the MR bit.
The microprocessor may either enforce a 1 (idle state) in MR, MX by setting the control bit MRC or
MXC (MOCR register) to 0, or enable the control of these bits internally by the W6692A according to
the Monitor channel protocol. Thus, before a data exchange can begin, the control bit MRC, or MXC
should be set to 1 by the microprocessor.
The relevant status bits are:
For the reception of Monitor data: MDR (Monitor Channel Data Received )
MER (Monitor
Channel End of Reception)
For the transmission of Monitor data: MDA (Monitor Channel Data Acknowledged )
MAB
(Monitor Channel Data Abort)
About the status bit MAC( Monitor Channel Transmit Active) indicates whether a transmission is
progress
.
If set MAC = 0,
the previous transmission has been terminated. Before starting a transmission,
the microprocessor should verify that the transmitter is inactive.
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