參數(shù)資料
型號(hào)： W6692ACD
英文描述： ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料
文件頁(yè)數(shù)： 39/101頁(yè)
文件大?。?/td> 851K
代理商： W6692ACD
W6692A
Publication Release Date: July 2000
- 39 -
Revision A1
7.7.2 Transmission of Frames in B Channel
A 128-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 64 or 96
bytes. The transmitter and receiver use the same FIFO threshold setting.
The transmit operations differ in both modes:
Transparent mode
:
In this mode, the following functions are performed by the transmitter automatically:
- Flag generation
- CRC generation
- Zero bit insertion
The fields such as address, control and information are provided by the microprocessor and are
stored in transmit FIFO. To start the frame transmission, the microprocessor issues a XMS (Transmit
Message Start) command. The transmitter requests another block of data via XFR interrupt when
more than a threshold length of vacancies are left in the FIFO.The micro-processor then writes up to
a threshold length of data into the FIFO and activates the subsequent transmission of the frame by a
XMS command too. The microprocessor indicates the end of the frame transmission by issuing XME
(Transmit Message End) and XMS commands at the same time. The transmitter then transmits all
the data left in the transmit FIFO and appends the CRC and closing flag. After this, a XFR interrupt is
generated.
The inter-frame time fill pattern can be programmed to 1's or flags.
During the frame transmission, the microprocessor reaction time for the XFR interrupt depends on the
FIFO threshold setting and B channel data rate. For example, it is 8 mS if the FIFO threshold is 64
and the B channel data rate is 64 kbps. If the microprocessor fails to responds within the given
reaction time, the transmit FIFO will be underrun. In this case, the W6692A will automatically reset
the transmitter and send the inter frame time fill pattern on B channel. The microprocessor is
informed about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The
microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS
command to re-transmit the data.
The microprocessor can abort a frame transmission by issuing a Transmitter Reset command (XRST
bit in Bn_CMDR register). The XRES command resets the transmitter and sends inter frame time fill
pattern on B channel. It also results in a transmit pool ready condition.
Extended transparent mode:
All the data in the transmit FIFO are transmitted without any modification, i.e. no flags and CRCs are
inserted, and no bit stuffing is performed.
Transmission is started by a XMS command. The transmitter requests another block of data via XFR
interrupt when more than a threshold length of vacancies are left in the FIFO. The microprocessor
相關(guān)PDF資料
PDF描述
W6692ACF ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
W6694A TE Mode S/T Controller with USB 1.1 Interface
W6694CD USB Bus ISDN S/T-Controller
W7020 Telecommunication IC
W722 Controller Miscellaneous - Datasheet Reference
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W6692ACF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC
W6694 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller
W6694A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface
W6694CD 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller
W66ARX-18 制造商:Magnecraft 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*