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參數(shù)資料
| 型號： | W6692ACD |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 45/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACD |
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W6692A
Publication Release Date: July 2000
- 45 -
Revision A1
There are two interrupt input pins : XINTIN0, XINTIN1. Whenever signal level changes (eith rising or
falling), a maskable interrupt is generated which in turn will make an interrupt request on PCI bus if it
is unmasked. The interrupt status bits are ISTA:XINT0, ISTA:XINT1. The mask bits are IMASK:
XINT0, IMASK:XINT1. In addition, the signal level can be read at bits SQR: XIND0, SQR; XIND1.
These pins can be used for monitor of SLIC hook state and/or DTMF data valid status.
The IO interface can be programmed as simple IO (PCTL: XMODE = 0) or 8-bit microprocessor
interface (PCTL: XMODE = 1). As simple IOs, the pin data are accessed via XADDR and XDATA
registers. The register data is output on the pin if its output enable bit is set, the read data reflects the
current level of pin. In this mode, a maximum of 11 IO ports are supported.
If programmed as 8-bit microprocessor mode, an 8-bit multiplexed bus is used to control peripheral
deveces. The address and data are multiplexed on XAD7-0. XALE is used for address latch and
XRDB, XWRB are used for read/write strobe. To access peripheral device, first write the desired
address in XADDR register and then read/write data at XDATA register. In this mode, a maximum of
256 byte ports can be supported by adding some glue TTLs on board.
8. REGISTER DESCRIPTIONS
Note
: For all the internal registers, only byte access is allowed in all cases.
8.1 Chip Control and D_ch HDLC Controller
TABLE 8.1 REGISTER ADDRESS MAP: CHIP CONTROL AND D CHANNEL HDLC
Section Offset Access Register Name
8.1.1
00/00
R
Description
D_RFIFO
D channel receive FIFO
8.1.2
04/01
W
D_XFIFO
D channel transmit FIFO
8.1.3
08/02
W
D_CMDR
D channel command register
8.1.4
0C/03
R/W
D_MODE
D channel mode control
8.1.5
10/04
R/W
TIMR1
Timer 1
8.1.6
14/05
R_clear
ISTA
Interrupt status register
8.1.7
18/06
R/W
IMASK
Interrupt mask register
8.1.8
1C/07 R_clear
D_EXIR
D channel extended interrupt
8.1.9
20/08
R/W
D_EXIM
D channel extended interrupt mask
8.1.10
24/09
R
D_XSTA
D channel
transmit
status
8.1.11
28/0A
R
D_RSTA
D channel receive status
8.1.12
2C/0B
R/W
D_SAM
D channel address mask 1
8.1.13
30/0C
R/W
D_SAP1
D channel individual SAPI 1
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