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參數(shù)資料
| 型號： | W6692ACD |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 36/101頁 |
| 文件大小： | 851K |
| 代理商： | W6692ACD |
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W6692A
- 36 -
For address recognition, the W6692A provides four programmable registers for individual SAPI and
TEI values, SAP1-2 and TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The
SAPG equals 02H(C/R = 1) or 00H(C/R = 0) which corresponds to SAPI = 0. The TEIG equals FFH
which corresponds to TEI = 127. Incoming frame with 1
st
address octet = (SAP1 or SAP2 or SAPG)
and 2
nd
address octet = (TEI1 or TEI2 or TEIG) will be stored in the receive FIFO, with flag and FCS
fields being discarded and stuffed bits being removed.
The valid address combinations are:
- SAP1 and TEI1
- SAP1 and TEI = 127
- SAP2 and TEI2
- SAP2 and TEI = 127
- SAPI = 0 and TEI1
- SAPI = 0 and TEI2
- SAPI = 0 and TEI = 127
The receive frame address comparisons can be disabled (masked) per bit basis by setting the
D_SAM and D_TAM registers, but comparisons with the SAPG or TEIG cannot be disabled.
7.6.2 Reception of Frames in D Channel
A 128-byte FIFO is provided in the receive direction. The data movement is handled by interrupts.
There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End
(D_RME). The D_RMR interrupt indicates that at least 64 bytes of data have been received and the
message/ frame is not ended. Upon D_RMR interrupt, the microprocessor reads out 64 bytes of data
from the FIFO. The D_RME interrupt indicates the last segment of a message or a message with
length
≤
64 bytes has been received. The length of data is less than or equal to 64 and is specified in
the D_RBCL register.
If the length of the last segment of message is 64, only D_RME interrupt is generated and the RBC5-
0 bits in D_RBCL register are 000000B.
The data between the opening flag and the CRC field are stored in D_RFIFO. For LAPD frame, this
includes the address field, control field and information field.
When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from
D_RFIFO and issues the Receive Message Acknowledgement command (D_CMDR: RACK bit) to
explicitly acknowledge the interrupt. The microprocessor must handle the interrupt before more than
64 bytes of data are received. This corresponds to a maximum microprocessor reaction time of 32
mS at 16 kbps data rate.
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a
"data overflow" interrupt and status bit.
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PDF描述 |
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| W6692ACF | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694A | TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | USB Bus ISDN S/T-Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
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| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W66ARX-18 | 制造商:Magnecraft 功能描述: |
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