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參數(shù)資料
| 型號(hào)： | W6692ACD |
| 英文描述： | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)線接口|基本|的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁(yè)數(shù)： | 16/101頁(yè) |
| 文件大?。?/td> | 851K |
| 代理商： | W6692ACD |
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W6692A
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7. FUNCTIONAL DESCRIPTIONS
7.1 Main Block Functions
The functional block diagram of W6692A is shown in Fig.6.1. The main function blocks are:
- Layer 1 function according to ITU-T I.430
- Serial Interface Bus (SIB)
- B channel switching
- GCI bus interface
- PCM port (x 2) and internal B channel switching
- D channel HDLC controller
- B channel HDLC controllers (x 2)
- PCI/microprocessor interface circuit
- Serial EEPROM interface for PCI Configuration purpose
- Peripheral control
The layer 1 function includes:
- S/T bus transmitter/receiver
- Timing recovery using Digital Phase Locked Loop (DPLL) circuit
- Layer 1 activation/deactivation, TE mode
- D channel access control
- Frame alignment
- Multi-frame synchronization
- Test functions
The serial interface bus performs the multiplexing/demultiplexing of D and 2B channels.
The B channel switching determines the connection between layer 1/GCI, layer 2 and PCM.
The GCI circuit is used to connect a U transceiver (slave mode) or other slave GCI device (master
mode).
The PCM port provides two 64 kbps clear channels to connect to PCM codec chips.
The D channel HDLC controller performs the LAPD (Link Access Procedure on the D channel)
protocol according to ITU-T I.441/Q.921 recommendation.
There are two independent B channel HDLC controllers. They can be used to support HDLC-like
protocols such as Internet PPP.
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