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參數(shù)資料
| 型號： | W89C880F |
| 英文描述： | LAN Hub Controller |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 23/72頁 |
| 文件大?。?/td> | 731K |
| 代理商： | W89C880F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 23 -
latched by the bit 3 of CMIIR, and be read by W89C840F. The application program can program bits
0, 1 and 2 of CMIIR to generate the chip select signal, clock and read command, based on the AC
timing spec. of the EEPROM device, to
EEPROM, and running over the pins EECS, BtAdata1/EECK,
and BtAdata2/EEDI respectively. For reading the output data from EEPROM, the application program
should make the necessary level transition as a clock on BtAdata1/EECK. One falling edge will trigger
the EEPROM device to drive the next bit of output data relative to the input command.
The EEPROM can be programmed through the general I/O port of the W89C840F. The
application program can write data into the EEPROM through programming the bits 0, 1 and 2 of the
register CMIIR. In the write cycle of the EEPROM device, the data on BtAdata3/EEDO is
meaningless.
BOOT ROM system read and software programming function
The W89C840F can address up to 256 Kbytes memory space for the on-board boot ROM
device. The on-board boot ROM device will be mapped into the host memory by the system BIOS
(Basic Input/Output System). After power-on reset, The BIOS will write a set of value with all 1 to the
F30/FERBA configuration register and then read the value back. The W89C840F will return the all 1
value, except some bits with 0, depending on the configuration of C48/CBRCR. The relationship
between the return value from the register F30/FERBA and the setting to the register C48/CBRCR is
described as the following table.
ROM size
C48/CBRCR configuration
F30/FERBA return value
No boot ROM
00000000H
00000000H
No boot ROM
00000001H
00000000H
8 Kbytes ROM
00000002H
FFFFE001H
16 Kbytes ROM
00000003H
FFFFC001H
32 Kbytes ROM
00000004H
FFFF8001H
64 Kbytes ROM
00000005H
FFFF0001H
128 Kbytes ROM
00000006H
FFFE0001H
256 Kbytes ROM
00000007H
FFFC0001H
According to the return value from the register F30/FERBA, The system BIOS can determine
how large the memory space is required and then writes the memory space base address back to the
register F30/FERBA. In the cases of no boot ROM, the system BIOS will write back all 0 back into
F30/FERBA.
The address decoder of W89C840F for accessing the on-board ROM me
mory w l l be enabl ed
i f both bi t 0 of F30/FERBA and
bit 1 of F04/FCS are set to high at the same time.
The on-board
boot ROM data will be fetched by W89C840F and loaded into the host memory. On the other hand, the
address decoder will be disabled if the bit 0 of F30/FERBA is reset to 0. Under this case, W89C840F will
ignore the C48/CBRCR, no matter what content it has.
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