參數(shù)資料
型號(hào)： W89C880F
英文描述： LAN Hub Controller
中文描述： 局域網(wǎng)集線器控制器
文件頁數(shù)： 47/72頁
文件大小： 731K
代理商： W89C880F
W89C840F
Publication Release Date:April 1997
Revision A1
- 47 -
C20/CFDCR Frame Discarded Counter Register
The register C20/CFDCR records the missed packet count and the FIFO overflow count.
Bit
Attribute
Bit name
Description
31
R
MRFO
More Receive FIFO Overflow
This bit is the overflow bit of the receive FIFO Overflow counter.
The actual number of the FIFO overflow must be more t
han the
number shown by the bi t
field RFOC if the MRFO is set to high.
This bit will be reset after a read operation
30:17
R
RFOC
Receive FIFO Overflow Counter
The RFOC indicates the number of the packets that are discarded
due to the receive FIFO overflow under the condition of the receive
buffer is not available. This counter
i s
reset after being read by the
driver program.
16
R
MMP
More Missed Packets
Overflow bit of Missed Packet Counter. The actual number of the
missed packet must be more t
han the number shown by the bi t
field MPC if MMP is set tot high. This bit
i s
reset after read by a
read operation.
15:0
R
MPC
Missed Packet Counter
The MPC indicates the number of packets that are discarded due to
the receive FIFO overflow which is caused by that the receive DMA
can not get sufficient utilizing on PCI bus, in which, the receive
data buffer is available for the current frame. Although there is a
receive data buffer available for the current frame, the received data
of the current frame in the FIFO can not be completely moved into
the data buffer in host memory before the receive FIFO is overflow
if the receive DMA can not get sufficient utilizing on PCI bus.
This counter
i s
reset after a read operation.
C24/CMIIR MII Management and ROM Register
The register C24/CMIIR
speci fi es
the control function and the data message passing for the on board
EEPROM and boot ROM device access.
The followed table described the MII management frame format:
MII Management Protocol
PRE
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
Read
1...1
01
10
AAAAA
RRRRR
Z0
16 bits
Z
Write
1...1
01
01
AAAAA
RRRRR
10
16 bits
Z
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