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參數(shù)資料
| 型號(hào)： | W89C880F |
| 英文描述： | LAN Hub Controller |
| 中文描述： | 局域網(wǎng)集線(xiàn)器控制器 |
| 文件頁(yè)數(shù)： | 48/72頁(yè) |
| 文件大小： | 731K |
| 代理商： | W89C880F |
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W89C840F
- 48 -
PRE:Preample, ST:Start of Frame, OP:Operation code, PHYAD:PHY address, REGAD:register address
TA:Turnaround.
The detailed timings for the read and the write operation, respectively, of the MII management
function are illustrated as the figure below. Each bits in the management data frame(MDIO) are
synchronized at the rising edge of the MII management clock(MDC)
Typical MDIO/MDC Read Cycle
high impedance(z)
z
....
Idle
Start Read
PHYAD
REGAD
TA
Data
Idle
1 0
Z 0
MDC
MDIO
....
Preamble
0 1
Typical MDIO/MDC Write Cycle
z
....
Idle
Start Write
PHYAD
REGAD
TA
Data
Idle
1 0
MDC
MDIO
....
Preamble
0 1
0 1
Bit
Attribute
Bit name
Description
31:20
R
---
Reserved. Fixed at 0.
19
R
MDI
MII Management Port Data Input
T
he MI mnagemnt i nput data on the MMDIOpi n dri
ve
n
by external PHY can be read from this bit when the MDSEL is
reset. The MDI reflects the logic level on the MIMDIO pin
instantly, no latching device is used for keeping the logic level
message.
18
R/W
MDSEL
MII Management Port Read/Write Select
The MMDIO
will be programmed as an i
nput pi n when reset
MDSEL
. On the other hand, the MIMDIO will
be an output pi n
i f set MDSEL
high.
17
R/W
MDO
MII Management Port Write Data
The state of the MDO will be directly output through the MIMDIO
pin when the MIMDIO is performing an output pin. The
physi cal
devi ce seri al l y put the
serial command into MDO
by
one bit
data one MII management clock. The accessed data sequence and
timing are shown as the diagram above .
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