參數(shù)資料
型號： W89C880F
英文描述： LAN Hub Controller
中文描述： 局域網(wǎng)集線器控制器
文件頁數(shù)： 37/72頁
文件大?。?/td> 731K
代理商： W89C880F
W89C840F
Publication Release Date:April 1997
Revision A1
- 37 -
C04/CTSDR Transmit Start Demand Register
The register C04/CTSDR is used to request the W89C840F to do a transmission process.
Bit
Attribute
Bit name
Description
31:0
W
TSD
Transmit Start Demand
A write to this register will trigger the W89C840F‘s transmit
DMA to fetch the descriptor for progressing the transmission
operation when the W89C840F’s transmit DMA is staying at the
suspend state. Otherwise, the write operation will have no effect.
The W89C840F‘s transmit DMA will return to the suspend state
if no descriptor is available. Meanwhile, the bit 2 of C14/CISR
will be asserted to claim the transmit buffer unavailable
If there is any descriptor available, W89C840F will start to the
transmit process.
C08/CRSDR Receive Start Demand Register
The register C04/CTSDR is used to request the W89C840F to do a receive process.
Bit
Attribute
Bit name
Description
31:0
W
RSD
Receive Start Demand
A write to this register will trigger the W89C840F‘s receive
DMA to fetch the descriptor for progressing the receiving
operation when the W89C840F’s receive DMA is staying at the
suspend state. Otherwise, the write operation will have no effect.
The W89C840F‘s receive DMA will return to the suspend state
if no descriptor is available. Meanwhile, the bit 7 of C14/CISR
will be asserted to claim the receive buffer unavailable.
If there is any descriptor available, W89C840F will start to the
receive process and waiting for the incoming frames.
C0C/CRDLA Receive Descriptors List Addresses
The regi sters C0C/CRDLA defi ne
the start address of the receive descriptor list. It should be updated
only when the receive DMA state machine is staying at the stop state.
Bit
Attribute
Bit name
Description
31:2
R/W
SRL
Start of Receive List.
1:0
R/W
MBZ
Must be written as 0 for long word alignment.
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