參數(shù)資料
型號(hào)： WED416S16030A10SI
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： TSOP2-54
文件頁(yè)數(shù)： 21/26頁(yè)
文件大?。?/td> 398K
代理商： WED416S16030A10SI
4
White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
WED416S16030A
OPERATING AC PARAMETERS
(VCC = 3.3V, TA = -40°C TO +85°C)
Parameter
Symbol
7
75
8
10
Unit
Notes
Clock Cycle Time
CAS latency = 3
tCC
7.5
8
10
ns
1
CAS latency = 2
7.5
8
10
1
Clock to Valid Output Delay
tSAC
5.4
6
7
ns
1,2
Output Data Hold Time
tOH
33
3
ns
2
Clock High Pulse Width
tCH
2.5
3
ns
3
Clock Low Pulse Width
tCL
2.5
3
ns
3
Input Setup Time
tSS
1.5
2
ns
3
Input Hold Time
tSH
0.8
1
ns
3
Clock to Output in Low-Z
tSLZ
11
1
ns
2
Clock to Output in High-Z
tSHZ
5.4
6
7
ns
Row Active to Row Active Delay
tRRD
15
20
ns
4
RAS to CAS Delay
tRCD
20
ns
4
Row Precharge Time
tRP
20
ns
4
Row Active Time
tRAS
45
50
ns
4
Row Cycle Time - Operation
tRC
65
70
ns
4
Last Data In to New Column Address Delay
tCDL
11
1
CLK
5
Last Data In to Row Precharge
tRDL
22
2
CLK
5
Last Data In to Burst Stop
tBDL
11
1
CLK
5
Column Address to Column Address Delay
tCCD
11
1
CLK
6
Number of Valid Output Data
CAS latency = 3
2
ea
7
CAS latency = 2
1
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns, (trise 2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise & tfall are longer than 1ns, [(trise + tfall)/2]-1ns should be added to the parameter.
4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding
up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
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