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參數(shù)資料
| 型號： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED416S16030A
NOTES:
1.CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being
applied to.
2.Both Banks must be idle otherwise it is an illegal action.
3.If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4.The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank
not being referenced by the Current State then the action may be legal depending on the state of that bank.
5.If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6.The minimum and maximum Active time (tRAS) must be satisfied.
7.The RAS to CAS Delay (tRCD) must occur before the command is given.
8.Address A10 is used to determine if the Auto Precharge function is activated.
9.The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
CURRENT STATE TRUTH TABLE (CONT.)
L
OPCode
ModeRegisterSet
ILLEGAL
L
H
X
AutoorSelfRefresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
RowAddress
BankActivate
ILLEGAL
Refreshing
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
BurstTermination
NoOperation;IdleaftertRC
L
H
X
NoOperation
NoOperation;IdleaftertRC
H
X
DeviceDeselect
NoOperation;IdleaftertRC
L
OPCode
ModeRegisterSet
ILLEGAL
L
H
X
AutoorSelfRefresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
ModeRegister
L
H
BA
RowAddress
BankActivate
ILLEGAL
Accessing
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
BurstTermination
ILLEGAL
L
H
X
NoOperation
No Operation; Idle after two clock cycles
H
X
DeviceDeselect
No Operation; Idle after two clock cycles
Current State
Command
Action
Notes
CE
RAS
CAS
WE
BA0,1
A11-12,
Description
A10/AP-A0
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| WED416S16030C10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C75SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C7SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S16030C8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4M x 16 Bits x 4 Banks Synchronous DRAM |
| WED416S8030A | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2Mx16x 4 Banks Synchronous DRAM |
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