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參數(shù)資料
| 型號(hào)： | WED416S16030A10SI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | TSOP2-54 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 398K |
| 代理商： | WED416S16030A10SI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED416S16030A
FIG. 2 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @ CAS
LATENCY=3, BURST LENGTH=1
RAS
CAS
ADDR
BA
DQM
tSS
tSH
A10/AP
CKE
CLOCK
CE
Cb
Cc
Rb
Ca
Ra
tSH
DQ
Row Active
Precharge
Read
Write
Read
Row Active
Db
Qc
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
tSS
tSH
tRCD
tRP
tRAS
tRCD
tSS
tSH
tSS
BS
Note 3
Note 4
Rb
Note 3
Note 2, 3
Note 2
Note 4
Note 2, 3
Ra
BS
Qa
tSH
tSS
tOH
tSAC
tSLZ
tSS
tSH
tSS
tSH
tRAC
tSS
tSH
tCCD
tCH
tCL
tCC
DON'T CARE
Note 2
3. Enable and disable auto precharge function are controlled by A10/AP in
read/write command.
4. A10/AP and BA0~BA1
control bank precharge
when precharge
command is asserted.
NOTES:
1. All input except CKE &
DQM can be don't care
when CE is high at the
CLK high going edge.
2. Bank active & read/write
are controlled by BA0~BA1.
BA0 BA1
Operation
0
Distribute auto precharge, leave bankAactive at end of burst.
0
1
Disable auto precharge, leave bank B active at end of burst.
1
0
Disable auto precharge, leave bank C active at end of burst.
1
Disable auto precharge, leave bank D active at end of burst.
0
Enable auto precharge, precharge bankAat end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
Enable auto precharge, precharge bank D at end of burst.
A10/AP
0
1
BA0 BA1 Active & Read/Write
0
Bank A
0
1
Bank B
1
0
Bank C
1
Bank D
A10/AP BA0 BA1 Precharge
0
Bank A
0
1
Bank B
0
1
0
Bank C
0
1
Bank D
1
x
All Banks
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