參數(shù)資料
型號(hào)： XC2S100-5FG256I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 35/99頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2.5V I-TEMP 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 176
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
40
R
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF primitive names is as follows.
OBUF_<slew_rate>_<drive_strength>
<slew_rate> is either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24). The default is slew rate limited with 12 mA drive.
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 17 summarizes the output compatibility requirements.
The LOC property can specify a location for the OBUF.
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure 39, typically implements 3-state outputs or
bidirectional I/O.
With no extension or property specified for the generic
OBUFT primitive, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUFT can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
LVTTL 3-state output buffers have selectable drive
strengths.
The format for LVTTL OBUFT primitive names is as follows.
OBUFT_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The Versatile I/O OBUFT placement restrictions require
that within a given VCCO bank each OBUFT share the same
output source drive voltage. Input buffers of any type and
output buffers that do not require VCCO can be placed within
the same VCCO bank.
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate primitive to the output net of the OBUFT
(PULLUP, PULLDOWN, or KEEPER).
The weak "keeper" circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a VREF have automatic
placement of a VREF in the bank with an OBUFT configured
with a weak "keeper" circuit. This restriction does not affect
most circuit design as applications using an OBUFT
configured with a weak "keeper" typically implement a
bidirectional I/O. In this case the IBUF (and the
corresponding VREF) are explicitly placed.
The LOC property can specify a location for the OBUFT.
IOBUF
Use the IOBUF primitive for bidirectional signals that
require both an input buffer and a 3-state output buffer with
an active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 40.
With no extension or property specified for the generic
IOBUF primitive, the assumed standard is LVTTL input
buffer and slew rate limited LVTTL with 12 mA drive strength
for the output buffer.
The LVTTL IOBUF can support one of two slew rate modes
to minimize bus transients. By default, the slew rate for each
output buffer is reduced to minimize power bus transients
when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF primitive names is as follows:
Table 17: Output Standards Compatibility
Requirements
Rule 1
Only outputs with standards which share
compatible VCCO may be used within the same
bank.
Rule 2
There are no placement restrictions for outputs
with standards that do not require a VCCO.
VCCO
Compatible Standards
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
2.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
1.5
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
Figure 39: 3-State Output Buffer Primitive (OBUFT
IO
I
IOBUFT
DS001_39_032300
T
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參數(shù)描述
XC2S1005FG456C 制造商:Xilinx 功能描述:
XC2S100-5FG456C 功能描述:IC FPGA 2.5V 600 CLB'S 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
XC2S100-5FG456I 功能描述:IC FPGA 2.5V I-TEMP 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC2S100-5FGG256C 功能描述:IC SPARTAN-II FPGA 100K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S100-5FGG256I 功能描述:IC SPARTAN-II FPGA 100K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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