參數(shù)資料
型號: XC2S100-5FG256I
廠商: Xilinx Inc
文件頁數(shù): 40/99頁
文件大?。?/td> 0K
描述: IC FPGA 2.5V I-TEMP 256-FBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-II
LAB/CLB數(shù): 600
邏輯元件/單元數(shù): 2700
RAM 位總計(jì): 40960
輸入/輸出數(shù): 176
門數(shù): 100000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
45
R
HSTL Class III
A sample circuit illustrating a valid termination technique for
HSTL_III appears in Figure 45. DC voltage specifications
appear in Table 23 for the HSTL_III standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
HSTL Class IV
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 46.DC voltage specifications
appear in Table 23 for the HSTL_IV standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
Figure 45: Terminated HSTL Class III
Table 23: HSTL Class III Voltage Specification
Parameter
Min
Typ
Max
VCCO
1.40
1.50
1.60
VREF (1)
-0.90
-
VTT
-VCCO
-
VIH
VREF + 0.1
-
VIL
--
VREF – 0.1
VOH
VCCO – 0.4
-
VOL
--
0.4
IOH at VOH (mA)
–8
-
IOL at VOL (mA)
24
-
Notes:
1.
Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
VREF = 0.9V
VCCO = 1.5V
50
Ω
Z = 50
HSTL Class III
DS001_45_061200
VTT = 1.5V
Figure 46: Terminated HSTL Class IV
Table 24: HSTL Class IV Voltage Specification
Parameter
Min
Typ
Max
VCCO
1.40
1.50
1.60
VREF
-0.90
-
VTT
-VCCO
-
VIH
VREF + 0.1
-
VIL
--
VREF – 0.1
VOH
VCCO – 0.4
-
VOL
--
0.4
IOH at VOH (mA)
–8
-
IOL at VOL (mA)
48
-
Notes:
1.
Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
VREF = 0.9V
VCCO = 1.5V
50
Ω
Z = 50
HSTL Class IV
DS001_46_061200
VTT = 1.5V
50
Ω
VTT = 1.5V
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