A" />
參數(shù)資料
型號(hào)： XC2S100-5FG456C
廠商： Xilinx Inc
文件頁數(shù)： 30/99頁
文件大?。?/td> 0K
描述： IC FPGA 2.5V 600 CLB'S 456-FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Spartan®-II
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 196
門數(shù)： 100000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
產(chǎn)品目錄頁面： 599 (CN2011-ZH PDF)
其它名稱： 122-1227
XC2S100-5FG456C-ND
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
36
R
At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x7E is invalid.
At the fourth rising edge of CLKA, a read operation is
performed at memory location 0x0F and invalid data is
present on the DOA bus. Port B also executes a read
operation to memory location 0x0F and also reads invalid
data.
At the fifth rising edge of CLKA a read operation is
performed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Initialization
The block RAM memory can initialize during the device
configuration sequence. The 16 initialization properties of
64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 14. Any
initialization properties not explicitly set configure as zeros.
Partial initialization strings pad with zeros. Initialization
strings greater than 64 hex values generate an error. The
RAMs can be simulated with the initialization values using
generics in VHDL simulators and parameters in Verilog
simulators.
Initialization in VHDL
The block RAM structures may be initialized in VHDL for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization.
Initialization in Verilog
The block RAM structures may be initialized in Verilog for
both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a
defparam to pass the initialization.
Block Memory Generation
The CORE Generator software generates memory
structures using the block RAM features. This program
outputs VHDL or Verilog simulation code templates and an
EDIF file for inclusion in a design.
For design examples and more information on using the
Block RAM, see XAPP173, Using Block SelectRAM+
Memory in Spartan-II FPGAs.
Using Versatile I/O
The Spartan-II FPGA family includes a highly configurable,
high-performance I/O resource called Versatile I/O to
provide support for a wide variety of I/O standards. The
Versatile I/O resource is a robust set of features including
programmable control of output drive strength, slew rate,
and input delay and hold time. Taking advantage of the
flexibility and Versatile I/O features and the design
considerations described in this document can improve and
simplify system level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for
high-performance I/O becomes more important. While
chip-to-chip delays have an increasingly substantial impact
on overall system speed, the task of achieving the desired
system performance becomes more difficult with the
proliferation of low-voltage I/O standards. Versatile I/O, the
revolutionary input/output resources of Spartan-II devices,
has resolved this potential problem by providing a highly
configurable, high-performance alternative to the I/O
resources of more conventional programmable devices.
The Spartan-II FPGA Versatile I/O features combine the
flexibility and time-to-market advantages of programmable
logic with the high performance previously available only
with ASICs and custom ICs.
Each Versatile I/O block can support up to 16 I/O standards.
Supporting such a variety of I/O standards allows the
Table 14: RAM Initialization Properties
Property
Memory Cells
INIT_00
255 to 0
INIT_01
511 to 256
INIT_02
767 to 512
INIT_03
1023 to 768
INIT_04
1279 to 1024
INIT_05
1535 to 1280
INIT_06
1791 to 1536
INIT_07
2047 to 1792
INIT_08
2303 to 2048
INIT_09
2559 to 2304
INIT_0a
2815 to 2560
INIT_0b
3071 to 2816
INIT_0c
3327 to 3072
INIT_0d
3583 to 3328
INIT_0e
3839 to 3584
INIT_0f
4095 to 3840
Table 14: RAM Initialization Properties
Property
Memory Cells
相關(guān)PDF資料
PDF描述
GBM06DRKN-S13 CONN EDGECARD 12POS .156 EXTEND
VI-21J-EU CONVERTER MOD DC/DC 36V 200W
LQG15HS56NJ02D INDUCTOR 56NH 200MA 0402
GBM06DRKH-S13 CONN EDGECARD 12POS .156 EXTEND
ADSP-BF531SBB400 IC DSP CTLR 16BIT 400MHZ 169-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S100-5FG456I 功能描述:IC FPGA 2.5V I-TEMP 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC2S100-5FGG256C 功能描述:IC SPARTAN-II FPGA 100K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S100-5FGG256I 功能描述:IC SPARTAN-II FPGA 100K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S100-5FGG456C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
XC2S100-5FGG456I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*