參數(shù)資料
型號(hào): XC2S300E-6PQ208C
廠商: Xilinx Inc
文件頁(yè)數(shù): 37/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V 1536 CLB'S 208-PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1536
邏輯元件/單元數(shù): 6912
RAM 位總計(jì): 65536
輸入/輸出數(shù): 146
門數(shù): 300000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1211
34
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100
Ω differential
load only. The VOH levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
HSTL I
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.61 VREF + 0.61
7.6
–7.6
SSTL2 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
15.2
–15.2
CTT
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
–0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note (2)
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2.
Tested according to the relevant specifications.
Symbol
Description
Conditions
Min
Typ
Max
Units
VCCO
Supply voltage
2.375
2.5
2.625
V
VOH
Output High voltage for Q and Q
RT = 100Ω across Q and Q signals
1.25
1.425
1.6
V
VOL
Output Low voltage for Q and Q
RT = 100Ω across Q and Q signals
0.9
1.075
1.25
V
VODIFF
Differential output voltage (Q – Q),
Q = High or (Q – Q), Q = High
RT = 100Ω across Q and Q signals
250
350
450
mV
VOCM
Output common-mode voltage
RT = 100Ω across Q and Q signals
1.125
1.25
1.375
V
VIDIFF
Differential input voltage (Q – Q),
Q = High or (Q – Q), Q = High
Common-mode input voltage = 1.25 V
100
350
-
mV
VICM
Input common-mode voltage
Differential input voltage =
±350 mV
0.2
1.25
2.2
V
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
DC Parameter
Min
Max
Min
Max
Min
Max
Units
VCCO
3.0
3.3
3.6
V
VOH
1.8
2.11
1.92
2.28
2.13
2.41
V
VOL
0.96
1.27
1.06
1.43
1.30
1.57
V
VIH
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
0.86
2.125
0.86
2.125
0.86
2.125
V
Differential input voltage
0.3
-
0.3
-
0.3
-
V
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