參數(shù)資料
型號: XC2S300E-6PQ208C
廠商: Xilinx Inc
文件頁數(shù): 8/108頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V 1536 CLB'S 208-PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1536
邏輯元件/單元數(shù): 6912
RAM 位總計: 65536
輸入/輸出數(shù): 146
門數(shù): 300000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1211
DS077-4 (v3.0) August 9, 2013
105
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L14N_YY
0
E10
All
-
I/O, L14N_YY
I/O
0
G10
-
I/O
I/O, L13P
0
A9
XC2S600E
-
I/O, L13P
I/O, L13P_Y
I/O, L13N
0
B9
XC2S600E
-
I/O, L13N
I/O, L13N_Y
I/O
0
H10
-
I/O
I/O, L12P_YY
0
C9
All
-
I/O, L12P_YY
I/O, L12N_YY
0
D9
All
-
I/O, L12N_YY
I/O
0
E9
-
I/O
I/O, VREF Bank 0,
L11P
0
F9
-
All
I/O, VREF Bank 0,
L11P
I/O, VREF Bank 0,
L11P
I/O, L11N
0
G9
-
I/O, L11N
I/O, L10P
0
A8
-
I/O, L10P
I/O, L10N
0
B8
-
I/O, L10N
I/O
0
H9
-
I/O
I/O, L9P
0
E8
XC2S600E
-
I/O
I/O, L9P_Y
I/O, L9N
0
F8
XC2S600E
-
I/O, VREF Bank 0,
L9N_Y
I/O, L8P
0
A7
XC2S600E
-
I/O, L8P
I/O, L8P_Y
I/O, L8N
0
B7
XC2S600E
-
I/O, L8N
I/O, L8N_Y
I/O
0
G8
-
I/O
I/O, L7P_YY
0
C7
All
-
I/O, L7P_YY
I/O, L7N_YY
0
D7
All
-
I/O, L7N_YY
I/O
0
E7
-
I/O
I/O, L6P_YY
0
F7
All
-
I/O, L6P_YY
I/O, VREF Bank 0,
L6N_YY
0
G7
All
I/O, VREF Bank 0,
L6N_YY
I/O, VREF Bank 0,
L6N_YY
I/O
0
A6
-
I/O
I/O, L5P
0
B6
-
I/O, L5P
I/O, L5N
0
C6
-
I/O, L5N
I/O, L4P
0
D6
-
I/O, L4P
I/O, L4N
0
E6
-
I/O, L4N
I/O
0
F6
-
I/O
I/O, L3P_YY
0
A5
All
-
I/O, L3P_YY
I/O, VREF Bank 0,
L3N_YY
0
B5
All
I/O, VREF Bank 0,
L3N_YY
I/O, VREF Bank 0,
L3N_YY
I/O, L2P_YY
0
D5
All
-
I/O, L2P_YY
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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