參數(shù)資料
型號(hào): XC2S300E-6PQ208C
廠(chǎng)商: Xilinx Inc
文件頁(yè)數(shù): 46/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V 1536 CLB'S 208-PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1536
邏輯元件/單元數(shù): 6912
RAM 位總計(jì): 65536
輸入/輸出數(shù): 146
門(mén)數(shù): 300000
電源電壓: 1.71 V ~ 1.89 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱(chēng): 122-1211
42
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Speed Grade
Units
-7
-6
Max
GCLK IOB and Buffer
TGPIO
Global clock pad to output
0.7
ns
TGIO
Global clock buffer I input to O output
0.45
0.5
ns
Symbol
Description
Standard
Speed Grade
Units
-7
-6
Data Input Delay Adjustments
TGPLVTTL
Standard-specific global clock
input delay adjustments
LVTTL
0
ns
TGPLVCMOS2
LVCMOS2
0
ns
TGPLVCMOS18
LVCMOS18
0.2
ns
TGPLVCDS
LVDS
0.38
ns
TGPLVPECL
LVCPECL
0.38
ns
TGPPCI33_3
PCI, 33 MHz, 3.3V
0.08
ns
TGPPCI66_3
PCI, 66 MHz, 3.3V
–0.11
ns
TGPGTL
GTL
0.37
ns
TGPGTLP
GTL+
0.37
ns
TGPHSTL
HSTL
0.27
ns
TGPSSTL2
SSTL2
0.27
ns
TGPSSTL3
SSTL3
0.27
ns
TGPCTT
CTT
0.33
ns
TGPAGP
AGP
0.27
ns
Notes:
1.
Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
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