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參數(shù)資料
| 型號： | XC2S300E-6PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 62/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 1536 CLB'S 208-PQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 1536 |
| 邏輯元件/單元數(shù)： | 6912 |
| RAM 位總計： | 65536 |
| 輸入/輸出數(shù)： | 146 |
| 門數(shù)： | 300000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1211 |
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DS077-4 (v3.0) August 9, 2013
57
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Low Voltage Differential Signals (LVDS
and LVPECL)
The Spartan-IIE family features low-voltage differential sig-
naling (LVDS and LVPECL). Each signal utilizes two pins on
the Spartan-IIE device, known as differential pin pairs. Each
differential pin pair has a Positive (P) and a Negative (N) pin.
These pairs are labeled in the following manner.
I/O, L#[P/N][-/_Y/_YY]
where
L = LVDS or LVPECL pin
# = Pin pair number
P = Positive
N = Negative
_Y = Asynchronous output allowed (device-dependent)
_YY = Asynchronous output allowed (all devices)
Synchronous or Asynchronous
I/O pins for differential signals can either be synchronous or
asynchronous,
input
or
output.
Differential
signaling
requires the pins of each pair to switch simultaneously. If the
output signals driving the pins are from IOB flip-flops, they
are synchronous. If the signals driving the pins are from
internal logic, they are asynchronous, and therefore more
care must be taken that they are simultaneous. Any differ-
ential pairs can be used for synchronous input and output
signals as well as asynchronous input signals.
However, only the differential pairs with the _Y or _YY suffix
can be used for asynchronous output signals.
Asynchronous Output Pad Name Designation
Because of differences between densities, the differential
pairs that can be used for asynchronous outputs vary by
device. The pairs that are available in all densities for a
given package have the _YY suffix. These pins should be
used for differential asynchronous outputs if the design may
later move to a different density. All other differential pairs
that can be used for asynchronous outputs have the _Y suf-
fix.
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. The "Pad Name" column leaves out the _Y suffix and
the "LVDS Asynchronous Output Option" column indicates
the densities that allow asynchronous outputs for LVDS or
LVPECL on the given pin.
DLL Pins
Pins labeled "I/O (DLL)" can be used as general-purpose
I/O or as inputs to the DLL. Adjacent DLL pins form a differ-
ential pair. They reside in two different banks, so if they are
outputs the VCCO level must be the same for both banks.
Each DLL pin can also be paired with the adjacent GCK
clock pin for a differential clock input. The "I/O (DLL)" pin
always becomes the N terminal when paired with GCK,
even if it is labeled "P" for its pairing with the adjacent DLL
pin.
VREF Pins
Pins labeled "I/O, VREF" can be used as either an I/O or a
VREF pin. If any I/O pin within the bank requires a VREF
input, all the VREF pins in the bank must be connected to
the same voltage. See the I/O banking rules in the Func-
tional Description module for more detail. If no pin in a
given bank requires VREF, then that bank's VREF pins can
be used as general I/O.
To simplify the following tables, the "Pad Name" column
shows the part of the name that is common across densi-
ties. When VREF is only available in limited densities, the
"Pad Name" column leaves out the VREF designation and
the "VREF Option" column indicates the densities that pro-
vide VREF on the given pin.
VCCO Banks
In the TQ144 and PQ208 packages, the eight banks have
VCCO connected together. Thus, only one VCCO is
allowed in these packages, although different VREF values
are allowed in each of the eight banks. See I/O Banking.
Available Differential Pairs According to
Package Type
Device
TQ144
PQ208
FT256
FG456
FG676
XC2S50E
28
50
83
-
XC2S100E
28
50
83
86
-
XC2S150E
-
50
83
114
-
XC2S200E
-
50
83
120
-
XC2S300E
-
50
83
120
-
XC2S400E
-
83
120
172
XC2S600E
-
120
205
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S300E-6PQ208I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 300K GATES 6912 CELLS 357MHZ 1.8V 208PQFP - Trays |
| XC2S300E-6PQG208C | 功能描述:IC SPARTAN-IIE FPGA 300K 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
| XC2S300E-6PQG208I | 功能描述:IC SPARTAN-IIE FPGA 300K 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S300E-6TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S300E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
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