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參數(shù)資料
| 型號(hào)： | XC3S1000-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 17/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1M STD 256-FTBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 1920 |
| 邏輯元件/單元數(shù)： | 17280 |
| RAM 位總計(jì)： | 442368 |
| 輸入/輸出數(shù)： | 173 |
| 門(mén)數(shù)： | 1000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E |
| 其它名稱(chēng)： | 122-1709 XC3S1000-4FTG256I-ND |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
113
X-Ref Target - Figure 41
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins used during the Master and Slave Parallel configuration modes,
sometimes also called the SelectMAP modes. In both Master and Slave Parallel configuration modes, D0-D7 form the
byte-wide configuration data input. See Table 75 for Mode Select pin settings required for Parallel modes.
As shown in Figure 41, D0 is the most-significant bit while D7 is the least-significant bit. Bits D0-D3 form the high nibble of
the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and VCCO_5 voltage supplies are required and must both equal the
voltage of the attached configuration device, typically either 2.5V or 3.3V.
Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte
presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B and
RDWR_B does not matter, although RDWR_B must be asserted throughout the configuration process. If RDWR_B is
de-asserted during configuration, the FPGA aborts the configuration operation.
After configuration, these pins are available as general-purpose user I/O. However, the SelectMAP configuration interface is
optionally available for debugging and dynamic reconfiguration. To use these SelectMAP pins after configuration, set the
Persist bitstream generation option.
The Readback debugging option, for example, requires the Persist bitstream generation option. During Readback mode,
assert CS_B Low, along with RDWR_B High, to read a configuration data byte from the FPGA to the D0-D7 bus on a rising
CCLK edge. During Readback mode, D0-D7 are output pins.
In all the cases, the configuration data and control signals are synchronized to the rising edge of the CCLK clock signal.
Table 71: Dual-Purpose Pins Used in Master or Slave Serial Mode
Pin Name
Direction
Description
DIN
Input
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and
all data is synchronized to the rising CCLK edge. After configuration, this pin is available as a user I/O.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
DOUT
Output
Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of one
FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in Slave Serial
mode—so that configuration data passes from one to the next, in daisy-chain fashion. This “daisy
chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error:
Just after power is applied, the FPGA produces a Low-to-High transition on this pin indicating that
initialization (i.e., clearing) of the configuration memory has finished. Before entering the User mode,
this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a High
logic level. In a multi-FPGA design, tie (wire AND) the INIT_B pins from all FPGAs together so that the
common node transitions High only after all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of configuration. This
action stalls the FPGA at the configuration step just before the mode select pins are sampled.
During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by asserting
INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
I/O Bank 4 (VCCO_4)
I/O Bank 5 (VCCO_5)
High Nibble
Low Nibble
Configuration Data Byte
D0
D1
D2
D3
D4
D5
D6
D7
0xFC =
1
0
(MSB)
(LSB)
Figure 41: Configuration Data Byte Mapping to D0-D7 Bits
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