- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19303 > XC3S1000-4FTG256I (Xilinx Inc)SPARTAN-3A FPGA 1M STD 256-FTBGA PDF資料下載
參數(shù)資料
| 型號： | XC3S1000-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 206/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1M STD 256-FTBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 1920 |
| 邏輯元件/單元數(shù)： | 17280 |
| RAM 位總計： | 442368 |
| 輸入/輸出數(shù)： | 173 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E |
| 其它名稱： | 122-1709 XC3S1000-4FTG256I-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁當(dāng)前第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
39
DFS Clock Output Connections
There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illustrated
in sections [a] and [c], respectively, of Figure 21. This is similar to what has already been described for the DLL component.
In the on-chip case, it is possible to connect either of the DFS’s two output clock signals through general routing resources
to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock
network. The optional feedback loop is formed in this way, routing CLK0 to a global clock net, which in turn drives the CLKFB
input.
In the off-chip case, the DFS’s two output clock signals, plus CLK0 for an optional feedback loop, can exit the FPGA using
output buffers (OBUF) to drive a clock network plus registers on the board. The feedback loop is formed by feeding the CLK0
signal back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global
clock net is connected directly to the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase of a DCM clock output signal relative to the CLKIN signal: First,
there are nine clock outputs that employ the DLL to achieve a desired phase relationship: CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKDV CLKFX, and CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in this section to provide a still finer degree of control. The PS
component is only available when the DLL is operating in its low-frequency mode. The PS component phase shifts the DCM
output clocks by introducing a "fine phase shift" (TPS) between the CLKFB and CLKIN signals inside the DLL component.
The user can control this fine phase shift down to a resolution of 1/256 of a CLKIN cycle or one tap delay (DCM_TAP),
whichever is greater. When in use, the PS component shifts the phase of all nine DCM clock output signals together. If the
PS component is used together with a DCM clock output such as the CLK90, CLK180, CLK270, CLK2X180 and CLKFX180,
then the fine phase shift of the former gets added to the coarse phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS component for use in addition to selecting between two operating
modes. As described in Table 20, this attribute has three possible values: NONE, FIXED and VARIABLE. When
CLKOUT_PHASE_SHIFT is set to NONE, the PS component is disabled and its inputs, PSEN, PSCLK, and PSINCDEC,
must be tied to GND. The set of waveforms in section [a] of Figure 22 shows the disabled case, where the DLL maintains a
zero-phase alignment of signals CLKFB and CLKIN upon which the PS component has no effect. The PS component is
enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase mode and the
Variable Phase mode, respectively. These two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to CLKIN by setting and/or adjusting the value of the PHASE_SHIFT
attribute. This value must be an integer ranging from –255 to +255. The PS component uses this value to calculate the
desired fine phase shift (TPS) as a fraction of the CLKIN period (TCLKIN). Given values for PHASE-SHIFT and TCLKIN, it is
possible to calculate TPS as follows:
TPS = TCLKIN(PHASE_SHIFT/256)
Equation 4
Both the Fixed Phase and Variable Phase operating modes employ this calculation. If the PHASE_SHIFT value is zero, then
CLKFB and CLKIN will be in phase, the same as when the PS component is disabled. When the PHASE_SHIFT value is
positive, the CLKFB signal will be shifted later in time with respect to CLKIN. If the attribute value is negative, the CLKFB
signal will be shifted earlier in time with respect to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of the TCLKIN, as determined by Equation 4 and its user-selected
PHASE_SHIFT value P. The set of waveforms insection [b] of Figure 22 illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK and PSINCDEC inputs are not used and
must be tied to GND. Fixed phase shift requires ISE software version 10.1.03 or later.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EMC43DRXH-S734 | CONN EDGECARD 86POS DIP .100 SLD |
| 6-5174681-7 | CONN D-PLUG FEM SCKT 68POS VERT |
| NCV8509PDW26R2 | IC REG LDO 5V/2.6V 16SOIC |
| TACL475M003H | CAP TANT 4.7UF 3V 20% 0603 |
| GBC22DRTN-S13 | CONN EDGECARD 44POS .100 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4PQG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。