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參數(shù)資料
| 型號(hào)： | XC3S1000-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 230/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1M STD 256-FTBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 1920 |
| 邏輯元件/單元數(shù)： | 17280 |
| RAM 位總計(jì)： | 442368 |
| 輸入/輸出數(shù)： | 173 |
| 門(mén)數(shù)： | 1000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E |
| 其它名稱： | 122-1709 XC3S1000-4FTG256I-ND |
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Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
60
Table 30: Power Voltage Ramp Time Requirements
Symbol
Description
Device
Package
Min
Max
Units
TCCO
VCCO ramp time for all eight banks
All
No limit(4)
–N/A
TCCINT
VCCINT ramp time, only if VCCINT is last in
three-rail power-on sequence
All
No limit
No limit(5)
N/A
Notes:
1.
If a limit exists, this specification is based on characterization.
2.
The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.
3.
For information on power-on current needs, see Power-On Behavior, page 54
4.
For mask revisions earlier than revision E (see Mask and Fab Revisions, page 58), TCCO min is limited to 2.0 ms for the XC3S200 and
XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and
FG packages.
5.
For earlier device versions with the FQ fabrication/process code (see Mask and Fab Revisions, page 58), TCCINT max is limited to 500 s.
Table 31: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain RAM data
1.0
V
VDRAUX
VCCAUX level required to retain RAM data
2.0
V
Notes:
1.
RAM contents include data stored in CMOS configuration latches.
2.
The level of the VCCO supply has no effect on data retention.
3.
If a brown-out condition occurs where VCCAUX or VCCINT drops below the retention voltage, then VCCAUX or VCCINT must drop below the
minimum power-on reset voltage indicated in Table 29 in order to clear out the device configuration content.
Table 32: General Recommended Operating Conditions
Symbol
Description
Min
Nom
Max
Units
TJ
Junction temperature
Commercial
0
25
85
°C
Industrial
–40
25
100
°C
VCCINT
Internal supply voltage
1.140
1.200
1.260
V
VCCO(1)
Output driver supply voltage
1.140
–
3.465
V
VCCAUX
Auxiliary supply voltage
2.375
2.500
2.625
V
ΔVCCAUX(2) Voltage variance on VCCAUX when using a DCM
–
–10
mV/ms
VIN(3)
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(4)(6)
VCCO = 3.3V, IO
–0.3
–3.75
V
–0.3
–3.75
V
VCCO ≤ 2.5V, IO
–0.3
V
–0.3
V
Voltage applied to all Dedicated pins relative to GND(5)
–0.3
V
Notes:
1.
The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range
specific to each of the single-ended I/O standards is given in Table 35, and that specific to the differential standards is given in Table 37.
2.
Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
3.
Input voltages outside the recommended range are permissible provided that the IIK input diode clamp diode rating is met. Refer to Table 28.
4.
Each of the User I/O and Dual-Purpose pins is associated with one of the VCCO rails. Meeting the VIN limit ensures that the internal diode
junctions that exist between these pins and their associated VCCO and GND rails do not turn on. The absolute maximum rating is provided
in Table 28.
5.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on.
6.
See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Generation FPGAs.
7.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.3V is supported but can cause increased leakage
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
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