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參數(shù)資料
| 型號(hào)： | XC3S1000-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 192/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1M STD 256-FTBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 1920 |
| 邏輯元件/單元數(shù)： | 17280 |
| RAM 位總計(jì)： | 442368 |
| 輸入/輸出數(shù)： | 173 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 配用： | 122-1502-ND - KIT STARTER SPARTAN-3 PCI-E |
| 其它名稱： | 122-1709 XC3S1000-4FTG256I-ND |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
271
Revision History
Date
Version
Description
04/03/2003
1.0
Initial Xilinx release.
04/21/2003
1.1
Added information on the VQ100 package footprint, including a complete pinout table (Table 87) and
footprint diagram (Figure 44). Updated Table 85 with final I/O counts for the VQ100 package. Also added
final differential I/O pair counts for the TQ144 package. Added clarifying comments to HSWAP_EN pin
description on page 119. Updated the footprint diagram for the FG900 package shown in Figure 55a and
Figure 55b. Some thick lines separating I/O banks were incorrect. Made cosmetic changes to Figure 40,
Figure 42, and Figure 43. Updated Xilinx hypertext links. Added XC3S200 and XC3S400 to Pin Name
column in Table 91.
05/12/2003
1.1.1
AM32 pin was missing GND label in FG1156 package diagram (Figure 53).
07/11/2003
1.1.2
Dual-Purpose Pin I/O Standard During Configuration section. Clarified references to Module 2. For
XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in Table 110, key, and package
drawing.
07/29/2003
1.2
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair names.
The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25, U26, V9, V10, V25,
V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected. Modified affected balls and
re-sorted rows in Table 110. Updated affected balls in Figure 53. Also updated ASCII and Excel electronic
versions of FG1156 pinout.
08/19/2003
1.2.1
Removed 100 MHz ConfigRate option in CCLK: Configuration Clock section and in Table 80. Added note
that TDO is a totem-pole output in Table 77.
10/09/2003
1.2.2
Some pins had incorrect bank designations and were improperly sorted in Table 93. No pin names or
functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins in Table 93. In
Figure 47, removed some extraneous text from pin 106 and corrected spelling of pins 45, 48, and 81.
12/17/2003
1.3
Added FG320 pin tables and pinout diagram (FG320: 320-lead Fine-pitch Ball Grid Array). Made cosmetic
changes to the TQ144 footprint (Figure 46), the PQ208 footprint (Figure 47), the FG676 footprint
(Figure 53), and the FG900 footprint (Figure 55). Clarified wording in Precautions When Using the JTAG
Port in 3.3V Environments section.
02/27/2004
1.4
Clarified wording in Using JTAG Port After Configuration section. In Table 81, reduced package height for
FG320 and increased maximum I/O values for the FG676, FG900, and FG1156 packages.
07/13/2004
1.5
Added information on lead-free (Pb-free) package options to the Package Overview section plus Table 81
and Table 83. Clarified the VRN_# reference resistor requirements for I/O standards that use single
termination as described in the DCI Termination Types section and in Figure 42b. Graduated from
Advance Product Specification to Product Specification.
08/24/2004
1.5.1
Removed XC3S2000 references from FG1156: 1156-lead Fine-pitch Ball Grid Array.
01/17/2005
1.6
Added XC3S50 in CP132 package option. Added XC3S2000 in FG456 package option. Added
XC3S4000 in FG676 package option. Added Selecting the Right Package Option section. Modified or
08/19/2005
1.7
Removed term “weak” from the description of pull-up and pull-down resistors. Added IDCODE Register
values. Added signal integrity precautions to CCLK: Configuration Clock and indicated that CCLK should
be treated as an I/O during Master mode in Table 79.
04/03/2006
2.0
Added Package Thermal Characteristics. Updated Figure 41 to make it a more obvious example. Added
detail about which pins have dedicated pull-up resistors during configuration, regardless of the
04/26/2006
2.1
Corrected swapped data row in Table 86. The Theta-JA with zero airflow column was swapped with the
Theta-JC column. Made additional notations on CONFIG and JTAG pins that have pull-up resistors during
configuration, regardless of the HSWAP_EN input.
05/25/2007
2.2
Note 1 to Table 103 about VREF for XC3S1500 in FG676.
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