參數(shù)資料
型號(hào): XCV405E-6FG676I
廠商: Xilinx Inc
文件頁(yè)數(shù): 17/118頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V 676-BGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計(jì): 573440
輸入/輸出數(shù): 404
門(mén)數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
Module 4 of 4
37
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
FG900 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A
√ in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Num-
bers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative func-
tion(s) not available when the pair is used as a differential
pair or differential clock.
NA
GND
AC8
NA
GND
H8
NA
GND
AD7
NA
GND
B8
NA
GND
AE6
NA
GND
G7
NA
GND
F6
NA
GND
AF5
NA
GND
E5
NA
GND
AG4
NA
GND
D4
NA
GND
V3
NA
GND
N3
NA
GND
C3
NA
GND
AK2
NA
GND
AH3
NA
GND
AC2
NA
GND
H2
NA
GND
B2
NA
GND
A2
NA
GND
AK1
NA
GND
AJ2
NA
GND
AJ1
NA
GND
A1
NA
GND
B1
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
Pair
Bank
P
Pin
N
Pin
AO
Other
Functions
GCLK LVDS
3
0
C15
A15
NA
IO LVDS 34
2
1
E15
E16
NA
IO LVDS 34
1
5
AK16
AH16
NA
IO LVDS 177
0
4
AJ16
AF16
NA
IO LVDS 177
IO LVDS
Total Pairs: 235, Asynchronous Output Pairs: 85
10
G8
D5
-
20
H9
A3
-
40
D6
A4
-
50
B5
E7
VREF
60
F8
A5
-
70
N11
D7
-
80
E8
G9
-
90
J11
A6
VREF
10
0
B7
C7
-
11
0
H10
C8
-
12
0
F10
G10
-
13
0
H11
A8
VREF
15
0
J12
B9
-
17
0
B10
G11
-
19
0
F11
H13
-
20
0
D11
E11
-
22
0
C11
F12
-
23
0
D12
A10
VREF
24
0
A11
E12
-
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