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參數(shù)資料
| 型號： | XCV405E-6FG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 34/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 676-BGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
18
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
1.
Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2.
Enter the Shift-DR (SDR) state
3.
Shift a configuration bitstream into TDI
4.
Return to Run-Test-Idle (RTI)
5.
Load the JSTART instruction into IR
6.
Enter the SDR state
7.
Clock TCK through the startup sequence
8.
Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.
Configuration Sequence
The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
The power-up timing of configuration signals is shown in
The corresponding timing characteristics are listed in
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and
Global Write Enable (GWE) signals are released. This per-
Figure 20: Power-Up Timing Configuration Signals
VALI
PROGRAM
Vcc
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
TPL
TICCK
ds022_020_071201
TPOR
INIT
Table 12:
Power-up Timing Characteristics
Description
Symbol
Value
Units
Power-on Reset1
TPOR
2.0
ms, max
Program Latency
TPL
100.0
μs, max
CCLK (output) Delay
TICCK
0.5
μs, min
4.0
μs, max
Program Pulse Width
TPROGRAM
300
ns, min
Notes:
1.
TPOR delay is the initialization time required after VCCINT
reaches the recommended operating voltage.
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