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參數(shù)資料
| 型號(hào)： | XCV405E-6FG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 94/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 676-BGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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DS025-4 (v3.0) March 21, 2014
Module 4 of 4
1
2000-2014 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Virtex-E Pin Definitions
0
Virtex-E 1.8 V Extended Memory
Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
00
Production Product Specification
R
Pin Name
Dedicated Pin
Direction
Description
GCK0, GCK1,
GCK2, GCK3
Yes
Input
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
Yes
Input
Mode pins are used to specify the configuration mode.
CCLK
Yes
Input or
Output
The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial
modes, and output in master-serial mode. After configuration, it is input only,
logic level = Don’t Care.
PROGRAM
Yes
Input
Initiates a configuration sequence when asserted Low.
DONE
Yes
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. The pin
becomes a user I/O after configuration.
BUSY/DOUT
No
Output
In SelectMAP mode, BUSY controls the rate at which configuration data is
loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
D7
No
Input or
Output
In SelectMAP mode, D0-7 are configuration data pins. These pins become
user I/Os after configuration unless the SelectMAP port is retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user I/O
after configuration.
WRITE
No
Input
In SelectMAP mode, the active-low Write Enable signal. The pin becomes a
user I/O after configuration unless the SelectMAP port is retained.
CS
No
Input
In SelectMAP mode, the active-low Chip Select signal. The pin becomes a
user I/O after configuration unless the SelectMAP port is retained.
TDI, TDO,
TMS, TCK
Yes
Mixed
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
DXN, DXP
Yes
N/A
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
VCCINT
Yes
Input
Power-supply pins for the internal core logic.
VCCO
Yes
Input
Power-supply pins for the output drivers (subject to banking rules)
VREF
No
Input
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-6FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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