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| 型號(hào)： | XCV405E-6FG676I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 58/118頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V 676-BGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
40
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Application Examples
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
Termination Examples
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
GTL
A sample circuit illustrating a valid termination technique for
GTL is shown in Figure 44. Table 23 lists DC voltage speci-
fications.
GTL+
A sample circuit illustrating a valid termination technique for
GTL+ appears in Figure 45. DC voltage specifications
appear in Table 24.
Figure 44: Terminated GTL
VREF = 0.8V
VTT = 1.2V
50
Ω
50
Ω
VCCO = N/A
Z = 50
GTL
x133_08_111699
VTT = 1.2V
Table 23:
GTL Voltage Specifications
Parameter
Min
Typ
Max
VCCO
-N/A
-
VREF = N × VTT1
0.74
0.8
0.86
VTT
1.14
1.2
1.26
VIH = VREF + 0.05
0.79
0.85
-
VIL = VREF – 0.05
-
0.75
0.81
VOH
--
-
VOL
-0.2
0.4
IOH at VOH(mA)
--
-
IOLat VOL(mA) at 0.4V
32
-
IOLat VOL(mA) at 0.2V
-
40
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
Figure 45: Terminated GTL+
Table 24:
GTL+ Voltage Specifications
Parameter
Min
Typ
Max
VCCO
--
-
VREF = N × VTT1
0.88
1.0
1.12
VTT
1.35
1.5
1.65
VIH = VREF + 0.1
0.98
1.1
-
VIL = VREF – 0.1
-
0.9
1.02
VOH
--
-
VOL
0.3
0.45
0.6
IOH at VOH (mA)
-
IOLat VOL (mA) at 0.6V
36
-
IOLat VOL (mA) at 0.3V
-
48
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
VREF = 1.0V
VTT = 1.5V
50Ω
VCCO = N/A
Z = 50
GTL+
x133_09_012400
50Ω
VTT = 1.5V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-6FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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