參數(shù)資料
型號: XCV405E-6FG676I
廠商: Xilinx Inc
文件頁數(shù): 62/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V 676-BGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
44
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
LVTTL
LVTTL requires no termination. DC voltage specifications
appears in Table 34.
LVCMOS2
LVCMOS2 requires no termination. DC voltage specifica-
tions appear in Table 35.
LVCMOS18
LVCMOS18 does not require termination. Table 36 lists DC
voltage specifications.
AGP-2X
The specification for the AGP-2X standard does not docu-
ment a recommended termination technique. DC voltage
specifications appear in Table 37.
Table 34:
LVTTL Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF
--
-
VTT
--
-
VIH
2.0
-
3.6
VIL
0.5
-
0.8
VOH
2.4
-
VOL
--
0.4
IOH at VOH (mA)
24
-
IOLat VOL (mA)
24
-
Note: VOLand VOH for lower drive currents sample tested.
Table 35:
LVCMOS2 Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF
--
-
VTT
--
-
VIH
1.7
-
3.6
VIL
0.5
-
0.7
VOH
1.9
-
VOL
--
0.4
IOH at VOH (mA)
12
-
IOLat VOL (mA)
12
-
Table 36:
LVCMOS18 Voltage Specifications
Parameter
Min
Typ
Max
VCCO
1.70
1.80
1.90
VREF
--
-
VTT
--
-
VIH
0.65 x VCCO
-1.95
VIL
– 0.5
-
0.2 x VCCO
VOH
VCCO – 0.4
-
VOL
--
0.4
IOH at VOH (mA)
–8
-
IOLat VOL (mA)
8
-
Table 37:
AGP-2X Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = N × VCCO(1)
1.17
1.32
1.48
VTT
--
-
VIH = VREF + 0.2
1.37
1.52
-
VIL = VREF – 0.2
-
1.12
1.28
VOH = 0.9 × VCCO
2.7
3.0
-
VOL = 0.1 × VCCO
-
0.33
0.36
IOH at VOH (mA)
Note 2
-
IOLat VOL (mA)
Note 2
-
Notes:
1.
N must be greater than or equal to 0.39 and less than or
equal to 0.41.
2.
Tested according to the relevant specification.
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