參數(shù)資料
型號: XCV405E-6FG676I
廠商: Xilinx Inc
文件頁數(shù): 85/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V 676-BGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v3.0) March 21, 2014
Module 3 of 4
13
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Description(1)
Symbol
Speed Grade
Units
Min
-8
-7
-6
Combinatorial Delays
F operand inputs to X via XOR
TOPX
0.32
0.68
0.8
ns, max
F operand input to XB output
TOPXB
0.35
0.65
0.8
0.9
ns, max
F operand input to Y via XOR
TOPY
0.59
1.07
1.4
1.5
ns, max
F operand input to YB output
TOPYB
0.48
0.89
1.1
1.3
ns, max
F operand input to COUT output
TOPCYF
0.37
0.71
0.9
1.0
ns, max
G operand inputs to Y via XOR
TOPGY
0.34
0.72
0.8
0.9
ns, max
G operand input to YB output
TOPGYB
0.47
0.78
1.2
1.3
ns, max
G operand input to COUT output
TOPCYG
0.36
0.60
0.9
1.0
ns, max
BX initialization input to COUT
TBXCY
0.19
0.36
0.51
0.57
ns, max
CIN input to X output via XOR
TCINX
0.27
0.50
0.6
0.7
ns, max
CIN input to XB
TCINXB
0.02
0.04
0.07
0.08
ns, max
CIN input to Y via XOR
TCINY
0.26
0.45
0.7
ns, max
CIN input to YB
TCINYB
0.16
0.28
0.38
0.43
ns, max
CIN input to COUT output
TBYP
0.05
0.10
0.14
0.15
ns, max
Multiplier Operation
F1/2 operand inputs to XB output via AND
TFANDXB
0.10
0.30
0.35
0.39
ns, max
F1/2 operand inputs to YB output via AND
TFANDYB
0.28
0.56
0.7
0.8
ns, max
F1/2 operand inputs to COUT output via AND
TFANDCY
0.17
0.38
0.46
0.51
ns, max
G1/2 operand inputs to YB output via AND
TGANDYB
0.20
0.46
0.55
0.7
ns, max
G1/2 operand inputs to COUT output via AND
TGANDCY
0.09
0.28
0.30
0.34
ns, max
Setup and Hold Times before/after Clock CLK
CIN input to FFX
TCCKX/TCKCX
0.47 / 0
1.0 / 0
1.2 / 0
1.3 / 0
ns, min
CIN input to FFY
TCCKY/TCKCY
0.49 / 0
0.92 / 0
1.2 / 0
1.3 / 0
ns, min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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