參數(shù)資料
型號: XCV405E-7FG676C
廠商: Xilinx Inc
文件頁數(shù): 107/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
Module 4 of 4
13
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
FG676 Fine-Pitch Ball Grid Array Package
XCV405E Virtex-E Extended Memory devices are available
in the FG676 fine-pitch BGA package. Pins labeled
I0_VREF can be used as either. If the pin is not used as
VREF, it can be used as general I/O. Immediately following
Table 3, see Table 4 for FG676 package Differential Pair
information.
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
0GCK3
E13
0IO
A6
0IO
B3
0IO
C6
0IO
C8
0IO
D5
0IO
G13
0IO_L0N_Y
C4
0
IO_L0P_Y
F7
0
IO_L1N_YY
G8
0
IO_L1P_YY
C5
0
IO_VREF_L2N_YY
D6
0
IO_L2P_YY
E7
0
IO_L3N
A4
0
IO_L3P
F8
0
IO_L4N
B5
0
IO_L4P
D7
0
IO_VREF_L5N_YY
E8
0
IO_L5P_YY
G9
0
IO_L6N_YY
A5
0
IO_L6P_YY
F9
0IO_L7N_Y
D8
0
IO_L7P_Y
C7
0IO_L8N_Y
B7
0
IO_L8P_Y
E9
0
IO_L9N
A7
0
IO_L9P
D9
0
IO_L10N
B8
0
IO_VREF_L10P
G10
0
IO_L11N_YY
C9
0
IO_L11P_YY
F10
0
IO_L12N_Y
A8
0
IO_L12P_Y
E10
0
IO_L13N_YY
G11
0
IO_L13P_YY
D10
0
IO_L14N_YY
B10
0
IO_L14P_YY
F11
0
IO_L15N
C10
0
IO_L15P
E11
0
IO_L16N_YY
G12
0
IO_L16P_YY
D11
0
IO_VREF_L17N_YY
C11
0
IO_L17P_YY
F12
0
IO_L18N_YY
A11
0
IO_L18P_YY
E12
0
IO_L19N_Y
D12
0
IO_L19P_Y
C12
0
IO_VREF_L20N_Y
A12
0
IO_L20P_Y
H13
0
IO_LVDS_DLL_L21N
B13
1GCK2
C13
1IO
A19
1IO
A20
1IO
A22
1IO
B23
1
IO_LVDS_DLL_L21P
F14
1
IO_L22N
E14
1
IO_L22P
F13
1
IO_L23N_Y
D14
1
IO_VREF_L23P_Y
A14
1
IO_L24N_Y
C14
1
IO_L24P_Y
H14
1
IO_L25N_YY
G14
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
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