參數(shù)資料
型號: XCV405E-7FG676C
廠商: Xilinx Inc
文件頁數(shù): 82/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v3.0) March 21, 2014
10
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Clock Distribution Switching Characteristics
I/O Standard Global Clock Input Adjustments
Description
Symbol
Speed Grade
Units
Min
-8
-7
-6
GCLK IOB and Buffer
Global Clock PAD to output.
TGPIO
0.38
0.7
ns, max
Global Clock Buffer I input to O output
TGIO
0.11
0.19
0.45
0.50
ns, max
Description(1)
Symbol
Standard
Speed Grade
Units
Min
-8
-7
-6
Data Input Delay Adjustments
Standard-specific global clock
input delay adjustments
TGPLVTTL
LVTTL
0.0
ns, max
TGPLVCMOS2
LVCMOS2
–0.02
0.0
ns, max
TGPLVCMOS18
LVCMOS2
0.12
0.20
ns, max
TGLVDS
LVDS
0.23
0.38
ns, max
TGLVPECL
LVPECL
0.23
0.38
ns, max
TGPPCI33_3
PCI, 33 MHz, 3.3 V
–0.05
0.08
ns, max
TGPPCI66_3
PCI, 66 MHz, 3.3 V
–0.05
–0.11
ns, max
TGPGTL
GTL
0.20
0.37
ns, max
TGPGTLP
GTL+
0.20
0.37
ns, max
TGPHSTL
HSTL
0.18
0.27
ns, max
TGPSSTL2
SSTL2
0.21
0.27
ns, max
TGPSSTL3
SSTL3
0.18
0.27
ns, max
TGPCTT
CTT
0.22
0.33
ns, max
TGPAGP
AGP
0.21
0.27
ns, max
Notes:
1.
Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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參數(shù)描述
XCV405E-7FG676I 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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