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| 型號(hào)： | XCV405E-7FG676C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 54/118頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
36
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
The LVTTL OBUFT additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL
3-state
output
buffers
have
selectable
drive
strengths.
The format for LVTTL OBUFT symbol names is as follows.
OBUFT_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The following list details variations of the OBUFT symbol.
OBUFT
OBUFT_S_2
OBUFT_S_4
OBUFT_S_6
OBUFT_S_8
OBUFT_S_12
OBUFT_S_16
OBUFT_S_24
OBUFT_F_2
OBUFT_F_4
OBUFT_F_6
OBUFT_F_8
OBUFT_F_12
OBUFT_F_16
OBUFT_F_24
OBUFT_LVCMOS2
OBUFT_PCI33_3
OBUFT_PCI66_3
OBUFT_GTL
OBUFT_GTLP
OBUFT_HSTL_I
OBUFT_HSTL_III
OBUFT_HSTL_IV
OBUFT_SSTL3_I
OBUFT_SSTL3_II
OBUFT_SSTL2_I
OBUFT_SSTL2_II
OBUFT_CTT
OBUFT_AGP
OBUFT_LVCMOS18
OBUFT_LVDS
OBUFT_LVPECL
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
The SelectI/O OBUFT placement restrictions require that
within a given VCCO bank each OBUFT share the same out-
put source drive voltage. Input buffers of any type and out-
put buffers that do not require VCCO can be placed within
the same VCCO bank.
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PUL-
LUP, PULLDOWN, or KEEPER).
The weak “keeper” circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a VREF have automatic place-
ment of a VREF in the bank with an OBUFT configured with
a weak “keeper” circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak “keeper” typically implement a bidirectional I/O.
In this case the IBUF (and the corresponding VREF) are
explicitly placed.
The LOC property can specify a location for the OBUFT.
IOBUF
Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 42.
The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.
The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF symbol names is as follows.
IOBUF_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
Figure 41: 3-State Output Buffer Symbol (OBUFT)
O
I
OBUFT
x133_05_111699
T
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-7FG676I | 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-7FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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