- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4220 > XCV405E-7FG676C (Xilinx Inc)IC FPGA 1.8V C-TEMP 676-FBGA PDF資料下載
參數(shù)資料
| 型號： | XCV405E-7FG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 52/118頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
35
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows.
OBUF_<slew_rate>_<drive_strength>
<slew_rate>
is
either
F
(Fast),
or
S
(Slow)
and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The following list details variations of the OBUF symbol.
OBUF
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four VCCO banks.
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 20 summarizes the Virtex-E output compatibility
requirements. The LOC property can specify a location for
the OBUF.
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure 41, typically implements 3-state outputs or bidirec-
tional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
O
I
OBUF
x133_04_111699
Table 20:
Output Standards Compatibility
Requirements
Rule 1
Only outputs with standards that share compatible
VCCO can be used within the same bank.
Rule 2
There are no placement restrictions for outputs
with standards that do not require a VCCO.
VCCO
Compatible Standards
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
2.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
1.5
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BR93L86RFVT-WE2 | IC EEPROM 16KBIT 2MHZ 8TSSOP |
| XCV405E-6FG676I | IC FPGA 1.8V 676-BGA |
| BR93L86RFVM-WTR | IC EEPROM 16KBIT 2MHZ 8MSOP |
| BR93L86RFV-WE2 | IC EEPROM 16KBIT 2MHZ 8SSOP |
| BR25L020FV-WE2 | IC EEPROM SER 2KB SPI BUS 8SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-7FG676I | 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-7FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。