參數(shù)資料
型號: XCV405E-7FG676C
廠商: Xilinx Inc
文件頁數(shù): 5/118頁
文件大小: 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 4 of 4
DS025-4 (v3.0) March 21, 2014
26
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
FG900 Fine-Pitch Ball Grid Array Package
The XCV812E Virtex-E Extended Memory devices are
available in the FG900 fine-pitch BGA package. Pins
labeled I0_VREF can be used as either. If the pin is not
used as VREF, it can be used as general I/O. Immediately
following Table 5, see Table 6 for FG900 package Differen-
tial Pair information.
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
0GCK3
C15
0IO
A7
0IO
A13
0IO
C9
0IO
C10
0IO
D10
0IO
E6
0IO
F7
0IO
F9
0IO
F15
0IO
G12
0IO
G15
0IO
H15
0IO
J10
0IO
K12
0
IO_VREF
A9
0IO_L1N_Y
D5
0
IO_L1P_Y
G8
0IO_L2N_Y
A3
0
IO_L2P_Y
H9
0
IO_L4N_YY
A4
0
IO_L4P_YY
D6
0
IO_VREF_L5N_YY
E7
0
IO_L5P_YY
B5
0IO_L6N
A5
0IO_L6P
F8
0IO_L7N
D7
0IO_L7P
N11
0
IO_L8N_YY
G9
0
IO_L8P_YY
E8
0
IO_VREF_L9N_YY
A6
0
IO_L9P_YY
J11
0
IO_L10N
C7
0
IO_L10P
B7
0
IO_L11N
C8
0
IO_L11P
H10
0
IO_L12N_YY
G10
0
IO_L12P_YY
F10
0
IO_VREF_L13N_YY
A8
0
IO_L13P_YY
H11
0
IO_L15N
B9
0
IO_L15P
J12
0
IO_L17N
G11
0
IO_L17P
B10
0
IO_L19N_Y
H13
0
IO_L19P_Y
F11
0
IO_L20N_Y
E11
0
IO_L20P_Y
D11
0
IO_L22N_YY
F12
0
IO_L22P_YY
C11
0
IO_VREF_L23N_YY
A10
0
IO_L23P_YY
D12
0
IO_L24N
E12
0
IO_L24P
A11
0
IO_L25N
G13
0
IO_L25P
B12
0
IO_L26N_YY
A12
0
IO_L26P_YY
K13
0
IO_VREF_L27N_YY
F13
0
IO_L27P_YY
B13
0
IO_L28N
G14
0
IO_L28P
E13
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
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