參數(shù)資料
型號(hào)： XR17L152IM
廠商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： CAP .068UF 400V PEN FILM 2825 5%
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 29/55頁(yè)
文件大?。?/td> 318K
代理商： XR17L152IM
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
29
4.6.3
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
4.6.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled during
powerup or reset by the EN485# pin or in software by FCTR bit-5. It de-asserts RTS# or DTR# after a specified
delay indicated in MSR[7:4] following
the last stop bit of the last character that has been transmitted. This helps
in turning around the transceiver to receive the remote station’s response. The delay optimizes the time
needed for the last transmission to reach the farthest station on a long cable network before switching off the
line driver. This delay prevents undesirable line signal disturbance that causes signal degradation. It also
changes the transmitter empty interrupt to TSR empty instead of THR empty.
Transmitter Operation in FIFO
4.7
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR bits 1-4 and an LSR interrupt is generated immediately if IER bit-2 is enabled. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the LSR bits are
immediately updated to reflect the status of the data byte in the RHR. The RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
Receiver
F
IGURE
13. T
RANSMIITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below Programmed Trigger
Level (TXTRG) and then
when becomes empty. FIFO
is Enabled by FCR bit-0=1
Transmit
FIFO
(64-Byte)
TXFIFO1
16X or 8X Clock
(8XMODE Register)
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
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