XR17V258
20
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
1.6.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
The XR17V258 has a general purpose 16-bit timer/counter. The crystal/clock at the XTAL1 input or an external
clock at the TMRCK input pin can be selected as the clock source for the timer/counter. The timer can be set to
be a single-shot for a one-time event or re-triggerable for a periodic signal. An interrupt may be generated
when the timer times out and will show up as a Channel 0 interrupt (see Table 8). It is controlled through 4
configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. The TIMERCNTL register provides the
Timer commands such as start/stop, as shown in Table 10 below. The time-out output of the Timer can also be
optionally routed to the MPIO[0] pin. The block diagram of the Timer/Counter circuit is shown below:
FIGURE 6. TIMER/COUNTER CIRCUIT
Timer Interrupt
Timer
Output
MPIOLVL[0]
0
1
0
1
Timer Interrupt
No Interrupt
MPIO[0]
TMRCK
OSC. CLOCK
TIMERCNTL
COMMANDS
16-Bit
Timer/Counter
Start/Stop
Timer Interrupt Enable/ Disable
Single shot/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
Clock Select
Route/De-route to MPIO[0]
TIMERMSB [31:24] and TIMERLSB [23:16]
The concatentaion of the 8-bit registers TIMERMSB and TIMERLSB forms a 16-bit value which decides the
time-out period of the Timer, per the following equation:
Timer output frequency = Timer input clock / 16-bit Timer value
The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero
(timer disabled) upon powerup and reset. The ’Reset Timer’ command does not have any effect on this
register.
TIMERMSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10
Bit-9 Bit-8
TIMERLSB Register
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1 Bit-0
16-Bit Timer/Counter Programmable Registers
TIMER [15:8] Reserved