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參數(shù)資料
| 型號： | XR17V258IV-0A-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17V258 144LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR17V258
28
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
generators for standard or custom rates. Typically, the oscillator connections are shown in Figure 10. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
FIGURE 10. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47pF
C2
22-47pF
14.7456
MHz
XTAL1
XTAL2
R=300K to 400K
3.0 TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in Table 5 set to ease
programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V258 supports
PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
3.1
FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT.
The XR17V258 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/
written to, as shown in Table 5. The following is an extract from the table showing the memory locations that
support burst transactions:
Channel N: (for channels 0 through 7) where M = 2N + 1.
RX FIFO
:
0xM00 - 0xM3F (64 bytes)
TX FIFO
:
0xM00 - 0xM3F (64 bytes)
RX FIFO + status
:
0xM80 - 0xMFF (64 bytes data + 64 bytes status)
For example, the locations for channel 2 are:
Channel 2:
RX FIFO
:
0x500 - 0x53F (64 bytes)
TX FIFO
:
0x500 - 0x53F (64 bytes)
RX FIFO + status
:
0x580 - 0x5FF (64 bytes data + 64 bytes status)
3.1.1
Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17V258IVF | 制造商:Exar Corporation 功能描述: |
| XR17V258IV-F | 功能描述:UART 接口集成電路 66MHz Octal PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V258IVTR-F | 功能描述:UART 接口集成電路 66MHz Octal PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V352 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUAL PCI EXPRESS UART |
| XR17V352IB-0A-EVB | 功能描述:界面開發(fā)工具 Eval Board for XR17V352IB Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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