- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16988 > XRD98L63EVAL (Exar Corporation)EVAL BOARD FOR XRD98L63 PDF資料下載
參數(shù)資料
| 型號： | XRD98L63EVAL |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XRD98L63 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
XRD98L63
18
Rev.1.01
Figure 9. Direct ADC Input Mode Timing
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based on pipeline
architecture with a built in track & hold input stage. The
track & hold and ADC conversion are controlled by the
externally supplied ADCLK.
The polarity of the ADCLK is programmable. If
ADCpol=low, the track & hold circuit tracks the PGA
output while ADCLK is high and holds while ADCLK is
low. If ADCpol=high, the track & hold circuit tracks the
PGA output while ADCLK is low and holds while ADCLK
is high. ADCLK should be a 50% duty cycle clock, and
should be synchronized with SBLK such that ADC
tracking ends at the same time as the CDS sample
black ends. (See Figure 16).
The ADC reference levels, Vcm, CapP & CapN, are
generated from an internal voltage reference. To mini-
mize noise, these pins should have high frequency
bypass capacitors to AGND. The value of these ca-
pacitors will affect the time required for the reference to
charge up and settle after power-down mode.
The ADC output bus, DB[11:0], has 3-state capability
controlled by the OE bit of the Control register and pin
42, OE. The output bus is enabled when both the OE bit
is high and the OE pin is low. The outputs become high
impedance when either the OE bit is low or the OE pin
is high.
Direct ADC Input Mode
The Direct ADC Input mode connects the CCDin &
REFin pins directly to the ADC inputs, by-passing the
CDS & PGA circuits. To enable the Direct ADC Input
mode, use the Serial Interface to program:
ADCin=1 in the Test register,
DOclamp=0 in the Clock register, and
MinClip=0 in the Control register.
In this mode, the PGA outputs are disabled so there is
no contention at the ADC input nodes. For best perfor-
mance, we recommend using fully differential signals
with a common mode level around 1.2V.
Input Signal
REFin-CCDin
ADCLK
Sample N
ADC tracks
Input Signal
DB[11:0]
Sample N+1
Data N-6
Data N-5
t
DL
Data N-7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 1589449-6 | STRIP CON |
| GBC43DCSH | CONN EDGECARD 86POS DIP .100 SLD |
| EBM22DTKD-S288 | CONN EDGECARD 44POS .156 EXTEND |
| 1-1499687-4 | AMPTRAC I/O 2MM CABLE 12POS 14FT |
| VI-25K-EY | CONVERTER MOD DC/DC 40V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L63ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L63AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRDAN27 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Compensating for Zero Order Hold Effects |
| XRDAN28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Frequency Response Effects of Overampling and Averaging on A/D Output Data |
| XRDAN29 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Criteria for Accurate Sampling of Analog Signals |
| XRDAN30 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。