Rev.1.01 XRD98L63 Figure 23. Line Rate Timing with CALonly=1 (CALpol=0, PBLKpol=0) Figure 22. Line Rate Timing with CALonly=0 (CLAMPpol=0, C" />
參數(shù)資料
型號: XRD98L63EVAL
廠商: Exar Corporation
文件頁數(shù): 22/41頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝: 1
系列: *
29
Rev.1.01
XRD98L63
Figure 23. Line Rate Timing with CALonly=1 (CALpol=0, PBLKpol=0)
Figure 22. Line Rate Timing with CALonly=0 (CLAMPpol=0, CALpol=0, PBLKpol=0)
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dumm y &
OB pixels
CAL
(optical black)
CLAMP
(DC restore)
CCD
Signal
Active Video
pixels
t
CAL
t
CLAMP
PBLK
(blanking)
D isconnect CDS
from input pins
If PBLK overlaps with CAL and/or CLAMP, it will not affect the optical black calibration and DC restore functions.
Internally, CAL & CLAMP will overwrite PBLK.
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dumm y &
OB pixels
CAL
Internal
(DC restore)
CCD
Signal
Active Video
pixels
t
CAL
4 pixels
PBLK
(blanking)
D isconnect CDS
from input pins
Internal
(optical black)
t
CAL
- 4 pixels
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