Rev.1.01 0 1 0 1 0 1 4 1 2 3 4 5 1 2 3 0 1 0 1 0 1 0 FSYNC EOS CCD PBLK CAL CLAMP * Line Pattern Select Exar Name TG Signal Name VD" />
參數(shù)資料
型號(hào): XRD98L63EVAL
廠商: Exar Corporation
文件頁(yè)數(shù): 26/41頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝: 1
系列: *
XRD98L63
32
Rev.1.01
0
1
0
1
0
1
4
1
2
3
4
5
1
2
3
0
1
0
1
0
1
0
FSYNC
EOS
CCD
PBLK
CAL
CLAMP
* Line Pattern
Select
Exar
Name
TG
Signal
Name
VD
ID
PBLK
OBCLP
CLPDM
1) PBLK latches EOS value into Line Pattern Select.
1)
Frame "N"
Frame "N+1"
CONDITIONS: FSYNCpol=0, PBLKpol=0, CALpol=0, CLAMPpol=0, EOSpol=1
* Internal signals
(Sony Progressive mode)
FSYNC
EOS
CCD
PBLK
CAL
CLAMP
4
1
2
3
4
5
1
2
3
* Line Pattern
Select
0
1
0
1
0
1
0
Exar
Name
TG
Signal
Name
VD
HD
PBLK
CPOB
MGstart = 0
1) FSYNC resets Line Pattern Select to "MGstart" bit value.
2) PBLK toggles Line Pattern Select value.
1)
2)
HCLR/CLPD
CONDITIONS: FSYNCpol=1, PBLKpol=1, CALpol=1, CLAMPpol=1, EOSpol=1
* Internal signals
(Panasonic Progresive mode)
MGstart = 1
Figure 25. Multiple Gain Mode Timing, Progressive, MGsel[1:0] = 01
Figure 26. Multiple Gain Mode Timing, Progressive, MGsel[1:0] = 11
MGsel
Functions
00
Sony Interlaced
01
Sony Progressive
10
Panasonic Interlaced
11
Panasonic Progressive
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