Rev.1.01 Aperture delays One of the most difficult tasks in designing a digital camera is optimizing the pixel timing for the CCD, " />
參數(shù)資料
型號(hào)： XRD98L63EVAL
廠商： Exar Corporation
文件頁(yè)數(shù)： 19/41頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝： 1
系列： *
XRD98L63
26
Rev.1.01
Aperture delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are three serial interface registers, SBLKdly,
SPIXdly, and ADCdly, used to program the aperture
delays. Each register is divided into 2 or 3 delay
parameters.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge of the external clock signals
(SBLK, SPIX & ADCLK) depends on the polarity
control bit for each clock. For the default case,
SBLKpol=0, SPIXpol=0 & ADCpol=0, the leading edge
is the falling edge and the trailing edge is the rising
edge.
The SBLKdly register is divided into two 3-bit delay
parameters, SBdly[2:0] and SBdly[5:3]. Each can add
from 0 to 7 ns of delay in 1 ns steps.
SBdly[2:0] controls the delay added to the leading
edge of SBLK. This positions the rising edge of the
internal signal
φ1.
SBdly[5:3] controls the delay added to the trailing edge
of SBLK. This positions the falling edge of the internal
signal
φ1.
The SPIXdly register is divided into three 3-bit delay
parameters, SPdly[2:0], SPdly[5:3] and SPdly[8:6].
Each can add from 0 to 7 ns of delay in 1 ns steps.
SPdly[2:0] controls the delay added to the leading
edge of SPIX. This positions the rising edge of the
internal signal
φ2.
SPdly[5:3] controls the delay added to the trailing edge
of SPIX. This positions the falling edge of the internal
signal
φ2.
SPdly[8:6] is only used when SPIXopt=1. It controls
the delay from the trailing edge of SBLK to the rising
edge of the internal signal
φ2. This delay is in addition
to SBdly[5:3], the SBLK trailing edge delay.
The ADCdly register is divided into two 4-bit delay
parameters, ADCdly[3:0] and ADCdly[7:5]. Each can
add from 0 to 7.5 ns of delay in 0.5 ns steps.
ADCdly[3:0] controls the delay added to the leading
edge of ADCLK. This positions the falling edge of the
internal signal
φ4.
ADCdly[7:4] controls the delay added to the trailing
edge of ADCLK. This positions the rising edge of the
internal signal
φ4.
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