Rev.1.01 Figure 17. Pixel Rate Clock Timing with SPIXopt=0 (Default) Figure 18. Pixel Rate Clock Timing with SPIXopt=1 SPIXopt In t" />
參數(shù)資料
型號： XRD98L63EVAL
廠商： Exar Corporation
文件頁數(shù)： 17/41頁
文件大小： 0K
描述： EVAL BOARD FOR XRD98L63
標準包裝： 1
系列： *
XRD98L63
24
Rev.1.01
Figure 17. Pixel Rate Clock Timing with SPIXopt=0 (Default)
Figure 18. Pixel Rate Clock Timing with SPIXopt=1
SPIXopt
In the default case (Figure 17) SPIXopt=0, the signal
controlling the internal Sample Video switches,
φ2, is
generated from only the SPIX pulse. This mode is
intended for camera systems where the designer has
the ability to externally fine tune both the rising and
falling edges of SPIX to achieve the best performance.
When SPIXopt = 1 (Figure 18),
φ2 is generated from a
combination of SBLK and SPIX.
φ2 will turn ON the
internal sample video switches by a programmed delay
after the SBLK pulse ends. The turn ON delay is
programmed by the addition of SBdly[5:3] and
SPdly[8:6].
φ2 will turn OFF the sample video switches
at the end of the SPIX pulse.
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ2
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ2
SBdly[5:3] + SPdlyB[8:6]
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