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參數(shù)資料
| 型號： | XRD98L63EVAL |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XRD98L63 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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17
Rev.1.01
XRD98L63
CDS By-Pass Mode
The CDS By-Pass mode connects the CCDin and
REFin pins directly to the CDS amp inputs, by-passing
the CDS switching function. This mode is useful for
testing the PGA/ADC with a simple differential or a
single-ended signal.
To enable the CDS By-Pass mode, write a “1” to the No
CDS bit in the Test register. This will disable the CDS
switching functions and turn on switches which connect
the CCDin & REFin pins directly to the CDS amp inputs.
In the CDS By-Pass mode, the SPIX signal is required
to clock the switched-capacitor PGA stages, and
ADCLK is required to clock the ADC. The PGA analog
output does not come out to any pin; the ADC digital
output must be monitored instead.
When using the CDS By-Pass mode, the calibration
logic must be put in either the Hold mode or the ManCal
mode. In the CDS By-Pass mode, the Coarse Offset
DAC does not affect the input, but the Fine Offset DAC
does affect the PGA output. The calibration logic is not
aware that the Coarse Offset DAC is not active, and will
cause errors if left operating in the automatic mode.
To simplify signal interfacing when using the CDS By-
Pass mode, write a “1” to the nofs2 bit in the Test
register. This will disable the scale offset introduced
at the PGA ouput (this offset is required for CCD signal
digitization).
When using the CDS By-Pass mode, the ADC digital
output code will be related to the inputs by the transfer
function below:
(
)
[
] (
)
CapN
CapP
2
4096
DAC
FineOffset
PGAgain
2048
ADCout
×
+
×
+
=
CCDin
REFin
Figure 8. CDS By-Pass Mode Timing
Input Signal
REFin-CCDin
SPIX
ADCLK
Sample N
PGA1 tracks
Input Signal
ADC tracks
PGA2 output
non-overlap
DB[11:0]
Sample N+1
Data N-7
Data N-6
PGA2 tracks
PGA1 output
t
DL
Data N-8
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