參數(shù)資料
型號： XRT75L00DIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PQFP52
封裝： 10 X 10 MM, TQFP-52
文件頁數(shù)： 6/92頁
文件大?。?/td> 894K
代理商： XRT75L00DIV
XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 28
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1................................................................................................ 28
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 29
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................. 29
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.............................................................................................................. 29
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: .......................................................................................................... 30
5.4.1 DS3/STS-1 LOS CONDITION:.................................................................................................................................... 30
D
ISABLING
ALOS/DLOS D
ETECTOR
:............................................................................................................30
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 30
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
REQEN (DS3
AND
STS-1
A
PPLICATIONS
)............................................................................................................................................................... 30
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 31
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775.......................................................................................... 31
F
IGURE
20. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775. ......................................................................................... 31
6.0 JITTER: ................................................................................................................................................32
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 32
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 32
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
............................................................................................................................ 32
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 33
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1................................................................................................................ 33
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3.............................................................................................................................. 33
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 34
6.3 JITTER GENERATION: .................................................................................................................................. 34
6.4 JITTER ATTENUATOR: ................................................................................................................................. 34
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)................................................................... 34
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATIONS
................................................................................................................................ 34
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 35
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 35
7.0 SERIAL HOST INTERFACE: ...............................................................................................................36
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
......................................................................................................................................... 36
T
ABLE
15: R
EGISTER
M
AP
AND
B
IT
N
AMES
.................................................................................................................................... 36
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
........................................................................................................................................ 37
T
ABLE
17: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
......................................................................................................................... 41
8.0 DIAGNOSTIC FEATURES: ..................................................................................................................42
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 42
8.2 LOOPBACKS: ................................................................................................................................................. 43
F
IGURE
25. PRBS MODE............................................................................................................................................................. 43
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 44
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 44
F
IGURE
26. A
NALOG
L
OOPBACK
..................................................................................................................................................... 44
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 45
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 45
F
IGURE
27. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 45
F
IGURE
28. R
EMOTE
L
OOPBACK
.................................................................................................................................................... 45
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS)...................................................................................................................................... 46
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ...............................................................47
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ............................ 47
F
IGURE
30. A S
IMPLE
I
LLUSTRATION
OF
A
DS3
SIGNAL
BEING
MAPPED
INTO
AND
TRANSPORTED
OVER
THE
SONET N
ETWORK
........ 48
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 49
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 49
9.2.1.1 A B
RIEF
D
ESCRIPTION
OF
AN
STS-1 F
RAME
......................................................................................................... 49
F
IGURE
31. A S
IMPLE
I
LLUSTRATION
OF
THE
SONET STS-1 F
RAME
.............................................................................................. 50
F
IGURE
32. A S
IMPLE
I
LLUSTRATION
OF
THE
STS-1 F
RAME
S
TRUCTURE
WITH
THE
TOH
AND
THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
51
F
IGURE
33. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 52
F
IGURE
34. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
.......................................................................................... 53
9.2.1.2 M
APPING
DS3
DATA
INTO
AN
STS-1 SPE ............................................................................................................ 54
F
IGURE
35. I
LLUSTRATION
OF
THE
B
YTE
S
TRUCTURE
OF
THE
STS-1 SPE....................................................................................... 54
F
IGURE
36. A
N
I
LLUSTRATION
OF
T
ELCORDIA
GR-253-CORE’
S
R
ECOMMENDATION
ON
HOW
MAP
DS3
DATA
INTO
AN
STS-1 SPE... 55
F
IGURE
37. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION
OF
T
ELCORDIA
GR-253-CORE’
S
R
ECOMMENDATION
ON
HOW
TO
MAP
DS3
DATA
INTO
AN
STS-1 SPE .............................................................................................................................................................. 55
9.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS......................................... 56
9.2.2.1 T
HE
I
DEAL
C
ASE
FOR
M
APPING
DS3
DATA
INTO
AN
STS-1 S
IGNAL
(
E
.
G
.,
WITH
NO
F
REQUENCY
O
FFSETS
) ............ 57
相關(guān)PDF資料
PDF描述
XRT75L02 TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L02IV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04DIV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L00DIV-F 功能描述:外圍驅(qū)動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L00DIVTR 功能描述:時(shí)鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L00DIVTR-F 功能描述:時(shí)鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L00ES 功能描述:時(shí)鐘合成器/抖動清除器 1CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L00IV 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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