In-Circuit Test Input
參數(shù)資料
型號(hào): XRT75R03IVTR-F
廠商: Exar Corporation
文件頁數(shù): 16/92頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
xr
XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.8
20
62
ICT
I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, set this pin
"High".
NOTE: This pin is internally pulled “High".
70
HOST/HW
I
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75R03 in HOST mode. Tie this “Low” to
configure in Hardware mode.
When the XRT75R03 is configured in HOST mode, the states of many of the dis-
crete input pins are controlled by internal register bits.
NOTE: This pin is internally pulled up.
CONTROL AND ALARM INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
122
RXA
****
External Resistor of 3.01K
± 1%.
Should be connected between RxA and RxB for internal bias.
123
RXB
****
External Resistor of 3.01K
± 1%.
Should be connected between RxA and RxB for internal bias.
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
44
JA0
I
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 42 configures the Jitter Attenuator as
shown in the table below.
NOTES:
1.
The setting of these input pins applies globally to all three (3) channels
in the XRT75R03.
2.
This input pin is ignored and should be tied to GND if the XRT75R03 is
configured to operate in the Host Mode.
GENERAL CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
1
Disable Jitter Attenuator
JA0
0
M ode
16 bit FIFO Depth
32 bit FIFO Depth
JA1
0
1
Disable Jitter Attenuator
0
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